公开(公告)号：US08751900B2

公开(公告)日：2014-06-10

申请号：US13106892

申请日：2011-05-13

申请人： Yong June Kim ,  Hong Rak Son ,  Seonghyeog Choi ,  Junjin Kong ,  Yongtaew Yim ,  Jaehong Kim ,  KyoungLae Cho ,  Wootae Chang

发明人： Yong June Kim ,  Hong Rak Son ,  Seonghyeog Choi ,  Junjin Kong ,  Yongtaew Yim ,  Jaehong Kim ,  KyoungLae Cho ,  Wootae Chang

IPC分类号： G11C29/00 ,  H03M13/00

CPC分类号： G06F11/106 ,  H03M13/1102 ,  H03M13/136 ,  H03M13/152 ,  H03M13/155 ,  H03M13/2909 ,  H03M13/618

摘要： A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.

摘要翻译： 存储装置包括从源区域输出读取数据的非易失性存储器装置和被配置为对读取数据中的多个向量执行ECC操作并将经纠错的读取数据写入到目标区域中的存储器控​​制器 非易失性存储器件。 存储器控制器声明对应于清洁区域的矢量是在纠错操作期间不使用多个矢量中的标志位的解码通过。

公开(公告)号：US09837156B2

公开(公告)日：2017-12-05

申请号：US14640653

申请日：2015-03-06

申请人： Changkyu Seol ,  Junjin Kong ,  JongHa Kim ,  Hyejeong So ,  Hong Rak Son ,  Seonghyeog Choi

发明人： Changkyu Seol ,  Junjin Kong ,  JongHa Kim ,  Hyejeong So ,  Hong Rak Son ,  Seonghyeog Choi

IPC分类号： G06F3/06 ,  G11C16/10 ,  G11C7/10 ,  G11C11/56

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/102

摘要： The operating method of the storage device includes receiving write data to be written at the plurality of memory cells; determining whether the received write data is LSB data to be written at the plurality of memory cells; and encoding the write data according to the determination. The write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells. The write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.

公开(公告)号：US09646706B2

公开(公告)日：2017-05-09

申请号：US15070122

申请日：2016-03-15

申请人： Hyejeong So ,  Junjin Kong ,  Changkyu Seol ,  Hong Rak Son ,  Seonghyeog Choi

发明人： Hyejeong So ,  Junjin Kong ,  Changkyu Seol ,  Hong Rak Son ,  Seonghyeog Choi

IPC分类号： G11C16/06 ,  G11C16/26 ,  G11C16/10 ,  G11C29/52 ,  H03M13/27 ,  H03M13/29 ,  H03M13/00 ,  G06F11/10 ,  G11C16/04 ,  G11C29/02 ,  G11C29/42 ,  G11C7/10

CPC分类号： G11C16/26 ,  G06F11/1048 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2789 ,  H03M13/2909 ,  H03M13/6508

摘要： An operating method is for a storage device that includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The operating method may include the memory controller receiving a read request from an external device, the memory controller adjusting a read scheme according to target data indicated by the read request among data of one page of the nonvolatile memory, and the memory controller reading the target data from the nonvolatile memory according to the adjusted read scheme.

公开(公告)号：US20140355348A1

公开(公告)日：2014-12-04

申请号：US14459736

申请日：2014-08-14

申请人： Yongjune KIM ,  Hong Rak SON ,  Seonghyeog CHOI ,  Junjin KONG

发明人： Yongjune KIM ,  Hong Rak SON ,  Seonghyeog CHOI ,  Junjin KONG

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  H01L27/1157 ,  H01L27/11582

摘要： Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.

摘要翻译： 提供一种闪速存储器系统及其字线交错方法。 闪存系统包括存储单元阵列和字线交错逻辑。 存储单元阵列连接到多个字线。 字线（WL）交织逻辑对与至少两个不同字线对应的WL数据和包括交错数据的编程数据执行对存储单元阵列的交织操作。

公开(公告)号：US20160034349A1

公开(公告)日：2016-02-04

申请号：US14713568

申请日：2015-05-15

申请人： SEONGHYEOG CHOI ,  CHANGKYU SEOL ,  JUNJIN KONG ,  YOUNGSUK RA ,  HONG RAK SON

发明人： SEONGHYEOG CHOI ,  CHANGKYU SEOL ,  JUNJIN KONG ,  YOUNGSUK RA ,  HONG RAK SON

IPC分类号： G06F11/10 ,  G11C29/52

CPC分类号： G06F11/1048 ,  G11C11/5642 ,  G11C29/021 ,  G11C29/028 ,  G11C29/26 ,  G11C2029/0411

摘要： A method of operating a nonvolatile memory device including a plurality of memory cells is provided. A default read operation is performed on a page using a default read voltage set to generate default raw data. If error bits of the default raw data are not corrected, a plurality of low-level read operations is performed on the page using a plurality of read voltage sets to generate a plurality of low-level raw data. Each read voltage set is different from the default voltage set. A read voltage set is selected from the plurality of read voltage sets as a starting voltage set, according to each low-level raw data. A high-level read operation using the selected starting voltage set is performed on the page to generate high-level raw data.

摘要翻译： 提供一种操作包括多个存储单元的非易失性存储器件的方法。 在使用默认读取电压设置的页面上执行默认读取操作以生成默认原始数据。 如果默认原始数据的错误位未被校正，则使用多个读取电压组在页面上执行多个低级读取操作，以生成多个低级原始数据。 每个读取电压设置与默认电压设置不同。 根据每个低级原始数据，从多个读取电压组中选择读取电压设置作为起始电压组。 在页面上执行使用所选择的启动电压设置的高电平读取操作，以生成高级原始数据。

公开(公告)号：US08996947B2

公开(公告)日：2015-03-31

申请号：US13598978

申请日：2012-08-30

申请人： Jungsoo Chung ,  Junjin Kong ,  Changkyu Seol ,  Hong Rak Son ,  Pilsang Yoon ,  Seonghyeog Choi

发明人： Jungsoo Chung ,  Junjin Kong ,  Changkyu Seol ,  Hong Rak Son ,  Pilsang Yoon ,  Seonghyeog Choi

IPC分类号： H03M13/00 ,  G06F11/10 ,  G11C11/56

CPC分类号： G06F11/1048 ,  G11C11/5628

摘要： A method generating program data to be stored in a nonvolatile memory device comprises randomizing the program data, and processing the randomized program data to reduce a frequency of at least one data state among the randomized program data.

摘要翻译： 一种生成要存储在非易失存储器件中的程序数据的方法包括随机化程序数据，并处理随机化的程序数据以减少随机化程序数据中的至少一个数据状态的频率。

公开(公告)号：US20160276035A1

公开(公告)日：2016-09-22

申请号：US15070122

申请日：2016-03-15

申请人： HYEJEONG SO ,  JUNJIN KONG ,  CHANGKYU SEOL ,  HONG RAK SON ,  SEONGHYEOG CHOI

发明人： HYEJEONG SO ,  JUNJIN KONG ,  CHANGKYU SEOL ,  HONG RAK SON ,  SEONGHYEOG CHOI

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C29/52 ,  H03M13/29 ,  G06F11/10 ,  G11C16/10 ,  H03M13/27

CPC分类号： G11C16/26 ,  G06F11/1048 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2789 ,  H03M13/2909 ,  H03M13/6508

摘要： An operating method is for a storage device that includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The operating method may include the memory controller receiving a read request from an external device, the memory controller adjusting a read scheme according to target data indicated by the read request among data of one page of the nonvolatile memory, and the memory controller reading the target data from the nonvolatile memory according to the adjusted read scheme.

摘要翻译： 操作方法是用于包括非易失性存储器和被配置为控制非易失性存储器的存储器控​​制器的存储设备。 操作方法可以包括存储器控制器从外部设备接收读取请求，存储器控制器根据由非易失性存储器的一页的数据中的读取请求指示的目标数据调整读取方案，并且读取目标的存储器控​​制器 来自非易失性存储器的数据根据​​调整后的读取方案。

公开(公告)号：US20160011807A1

公开(公告)日：2016-01-14

申请号：US14640653

申请日：2015-03-06

申请人： Changkyu SEOL ,  Junjin KONG ,  JongHa KIM ,  Hyejeong SO ,  Hong Rak SON ,  Seonghyeog CHOI

发明人： Changkyu SEOL ,  Junjin KONG ,  JongHa KIM ,  Hyejeong SO ,  Hong Rak SON ,  Seonghyeog CHOI

IPC分类号： G06F3/06

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/102

摘要： The operating method of the storage device includes receiving write data to be written at the plurality of memory cells; determining whether the received write data is LSB data to be written at the plurality of memory cells; and encoding the write data according to the determination. The write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells. The write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.

摘要翻译： 存储装置的操作方法包括：接收要写入多个存储单元的写入数据; 确定所接收的写入数据是否要被写入所述多个存储器单元的LSB数据; 以及根据确定对写入数据进行编码。 当写入数据是要写入多个存储器单元的LSB数据时，根据写入数据对写入数据进行编码。 当写入数据不是要写入多个存储器单元的LSB数据时，写数据根据写数据和要写入多个存储单元的写数据的较低数据的编码数据进行编码。

公开(公告)号：US08811080B2

公开(公告)日：2014-08-19

申请号：US13236176

申请日：2011-09-19

申请人： Yongjune Kim ,  Hong Rak Son ,  Seonghyeog Choi ,  Junjin Kong

发明人： Yongjune Kim ,  Hong Rak Son ,  Seonghyeog Choi ,  Junjin Kong

IPC分类号： G11C11/06

CPC分类号： G11C16/10 ,  G11C16/0483 ,  H01L27/1157 ,  H01L27/11582

摘要： Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.

摘要翻译： 提供一种闪速存储器系统及其字线交错方法。 闪存系统包括存储单元阵列和字线交错逻辑。 存储单元阵列连接到多个字线。 字线（WL）交织逻辑对与至少两个不同字线对应的WL数据和包括交错数据的编程数据执行对存储单元阵列的交织操作。

公开(公告)号：US08711624B2

公开(公告)日：2014-04-29

申请号：US13236249

申请日：2011-09-19

申请人： Seonghyeog Choi ,  Hong Rak Son ,  Junjin Kong ,  Jaehong Kim ,  KyoungLae Cho ,  Yong June Kim

发明人： Seonghyeog Choi ,  Hong Rak Son ,  Junjin Kong ,  Jaehong Kim ,  KyoungLae Cho ,  Yong June Kim

IPC分类号： G11C11/34

CPC分类号： G11C11/5621 ,  G11C16/10 ,  G11C16/3404

摘要： A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.

摘要翻译： 存储器装置包括存储单元阵列，配置成使用交织方案将数据进行交错和加载到缓冲电路中的自交织器以及被配置为控制对存储单元阵列中的交错数据的编程的控制逻辑。