公开(公告)号：US20080099821A1

公开(公告)日：2008-05-01

申请号：US11618675

申请日：2006-12-29

申请人： Jum Soo Kim ,  Seok Kiu Lee

发明人： Jum Soo Kim ,  Seok Kiu Lee

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A method of manufacturing semiconductor devices includes providing a semiconductor substrate including first active areas and isolation areas alternately arranged to be parallel to each other and second active areas connecting the first active areas to each other. A tunnel insulating layer, a charge storage layer, and an isolation mask are formed on the semiconductor substrate. The isolation mask, the charge storage layer, the tunnel insulating layer, and the semiconductor substrate are etched to form a trench on the isolation area. An isolation structure is formed on the trench. A dielectric layer, a conductive layer for a control gate, and a hard mask are sequentially formed on a structure that includes the isolation structure. The hard mask, the conductive layer for the control gate, the dielectric layer, and the charge storage layer are patterned to form drain select lines, word lines and source select lines intersecting the first active area. Junction areas are formed on the first active areas through an ion implanting process. A common source is formed on the first active areas and the second active area between adjacent source select lines.

摘要翻译： 一种制造半导体器件的方法包括提供半导体衬底，该半导体衬底包括交替布置为彼此平行的第一有源区和隔离区以及将第一有源区彼此连接的第二有源区。 隧道绝缘层，电荷存储层和隔离掩模形成在半导体衬底上。 蚀刻隔离掩模，电荷存储层，隧道绝缘层和半导体衬底，以在隔离区域上形成沟槽。 隔离结构形成在沟槽上。 介电层，用于控制栅极的导电层和硬掩模依次形成在包括隔离结构的结构上。 将硬掩模，用于控制栅极的导电层，电介质层和电荷存储层图案化以形成与第一有源区相交的漏极选择线，字线和源选择线。 通过离子注入工艺在第一有源区上形成接合区域。 在相邻的源选择线之间的第一有源区和第二有源区上形成公共源。

公开(公告)号：US07320915B2

公开(公告)日：2008-01-22

申请号：US11139059

申请日：2005-05-27

申请人： Seok Kiu Lee

发明人： Seok Kiu Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L29/513

摘要： The present invention relates to a method of manufacturing a flash memory device. According to the method of manufacturing the flash memory device, a gate line is formed to have a structure in which a tunnel oxide film, a polysilicon layer for floating gate, dielectric films and a polysilicon layer for a control gate are stacked, etch damages are compensated for by means of an oxidization process, and a metal layer formed on the polysilicon layer for control gate is formed by means of a damascene process. Accordingly, it is possible to sufficiently compensate for etch damages, prevent generation of abnormal oxidization in a metal layer, and improve the reliability of a process and electrical characteristics of a device accordingly.

摘要翻译： 本发明涉及一种制造闪速存储器件的方法。 根据制造闪速存储器件的方法，栅极线被形成为具有隧道氧化物膜，用于浮置栅极的多晶硅层，电介质膜和用于控制栅极的多晶硅层堆叠的结构，蚀刻损伤是 通过氧化处理进行补偿，并且通过镶嵌工艺形成用于控制栅极的在多晶硅层上形成的金属层。 因此，可以充分地补偿蚀刻损伤，防止金属层中的异常氧化的产生，并且相应地提高工艺的可靠性和电气特性。

公开(公告)号：US06979633B2

公开(公告)日：2005-12-27

申请号：US10704231

申请日：2003-11-07

申请人： Seok Kiu Lee ,  Il Wook Kim

发明人： Seok Kiu Lee ,  Il Wook Kim

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/223 ,  H01L21/285 ,  H01L21/306 ,  H01L21/311 ,  H01L21/324 ,  H01L21/768 ,  H01L21/425

CPC分类号： H01L21/324 ,  H01L21/02063 ,  H01L21/2236 ,  H01L21/28512 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828

摘要： Disclosed is a method of manufacturing a semiconductor device, which prevents a contact resistance due to a native oxide film from being increased. Semiconductor substrate on which a lower structure having a junction region is formed is prepared. Interlayer dielectric film is formed over a whole surface of semiconductor substrate. Contact hole exposing the junction region is formed by etching interlayer dielectric film. Dry-cleaning and wet-cleaning for a substrate surface exposed by the contact hole are sequentially performed. Washed contact surface is preliminarily treated under reducing gas atmosphere to remove a native oxide film formed on contact surface. Impurity is additionally doped to a surface of the junction region in-situ so that impurity damages on preliminary-treated contact surface are compensated for. Conductive film is deposited on the contact hole and the interlayer dielectric film in-situ.

摘要翻译： 公开了一种制造半导体器件的方法，其防止由于自然氧化物膜引起的接触电阻增加。 制备其上形成有结区的下部结构的半导体衬底。 层间电介质膜形成在半导体衬底的整个表面上。 通过蚀刻层间绝缘膜形成露出接合区域的接触孔。 依次进行由接触孔暴露的基板表面的干洗和湿清洗。 在还原气体气氛下预先处理洗涤的接触表面以除去在接触表面上形成的自然氧化膜。 杂质再附加地掺杂到接合区域的表面，从而补偿预处理的接触表面上的杂质损失。 导电膜原位沉积在接触孔和层间电介质膜上。

公开(公告)号：US06979616B2

公开(公告)日：2005-12-27

申请号：US10878346

申请日：2004-06-29

申请人： Se-Aug Jang ,  Heung-Jae Cho ,  Kwan-Yong Lim ,  Hyo-Geun Yoon ,  Seok-Kiu Lee ,  Hyun-Chul Sohn

发明人： Se-Aug Jang ,  Heung-Jae Cho ,  Kwan-Yong Lim ,  Hyo-Geun Yoon ,  Seok-Kiu Lee ,  Hyun-Chul Sohn

IPC分类号： H01L21/31 ,  H01L21/336 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11573

摘要： Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for the NVDRAM and a peripheral circuit region for a logic circuit; forming a mask on the cell region; performing a first wet etching process by using the mask as an etch barrier to remove the second oxide layer formed in the peripheral circuit region; performing a second wet etching process by using the second oxide layer remaining in the cell region as an etch barrier to remove the nitride layer formed in the peripheral circuit region; forming a third oxide layer on the first oxide layer remaining in the peripheral circuit region; and forming a gate electrode on the second oxide layer and the third oxide layer.

公开(公告)号：US06887788B2

公开(公告)日：2005-05-03

申请号：US10703745

申请日：2003-11-07

申请人： Jun Hee Cho ,  Il Wook Kim ,  Seok Kiu Lee ,  Tae Hang Ahn ,  Sung Eon Park

发明人： Jun Hee Cho ,  Il Wook Kim ,  Seok Kiu Lee ,  Tae Hang Ahn ,  Sung Eon Park

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/60 ,  H01L21/4763

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76897 ,  Y10S438/906

摘要： Disclosed is a method of manufacturing a semiconductor device. The method comprises the steps of: preparing a silicon substrate having a predetermined lower structure including a gate and a bonding area; forming an interlayer dielectric film on the top side of the substrate; forming a photosensitive film pattern, which exposes an area for providing contact, on the interlayer dielectric film; forming a contact hole exposing a bonding area of the substrate by etching the exposed part of the interlayer dielectric film; removing the photosensitive film pattern; performing a dry cleaning on the exposed bonding area of the substrate so that CF based polymer formed in the etching step is removed; and performing a nitrogen-hydrogen plasma processing on the surface of the exposed bonding area of the substrate so that oxygen polymer and remaining CF-based polymer are removed. Therefore, since hydrogen plasma processing is performed after contact etching, ohmic contact characteristics can be secured. In addition, since the hydrogen plasma processing is performed using a conventional photosensitive film strip apparatus, cost required to install and maintain an additional apparatus is not generated.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：制备具有包括栅极和接合区域的预定下部结构的硅衬底; 在所述基板的上侧形成层间电介质膜; 在所述层间绝缘膜上形成曝光用于提供接触的区域的感光膜图案; 通过蚀刻所述层间电介质膜的暴露部分形成暴露所述衬底的接合区域的接触孔; 去除感光膜图案; 在基板的暴露的接合区域上进行干洗，从而去除在蚀刻步骤中形成的CF基聚合物; 并在衬底的暴露的接合区域的表面上进行氮 - 氢等离子体处理，从而除去氧聚合物和剩余的CF基聚合物。 因此，由于在接触蚀刻之后进行氢等离子体处理，因此可以确保欧姆接触特性。 此外，由于使用传统的感光膜条装置执行氢等离子体处理，所以不会产生安装和维护附加装置所需的成本。

公开(公告)号：US06784031B2

公开(公告)日：2004-08-31

申请号：US10324720

申请日：2002-12-19

申请人： Sung Jae Joo ,  Seok Kiu Lee

发明人： Sung Jae Joo ,  Seok Kiu Lee

IPC分类号： H01L2100

CPC分类号： C23C16/46

摘要： Methods for forming thin films of semiconductor devices, and more specifically, methods for forming thin films of semiconductor devices, wherein the semiconductor substrate is subjected to a thin film formation process in a thin film formation apparatus containing a chamber, a susceptor vertically movable in the chamber and a heater disposed within the susceptor, the method comprising a preheating process for stabilizing the internal temperature of the chamber by vertically moving the susceptor a predetermined number of times prior to the thin film formation process.

摘要翻译： 用于形成半导体器件的薄膜的方法，更具体地，用于形成半导体器件的薄膜的方法，其中半导体衬底在包含腔室的薄膜形成设备中进行薄膜形成工艺，可在 室和设置在基座内的加热器，该方法包括预热过程，用于通过在薄膜形成过程之前将基座垂直移动预定次数来稳定室的内部温度。

公开(公告)号：USRE45232E1

公开(公告)日：2014-11-04

申请号：US13568920

申请日：2012-08-07

申请人： Dae Hee Weon ,  Seok Kiu Lee

发明人： Dae Hee Weon ,  Seok Kiu Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/76895

摘要： A method of manufacturing a semiconductor device having the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a selective silicon layer in the contact hole, and forming a selective conductive plug on the selective silicon layer.

摘要翻译： 一种制造半导体器件的方法，具有以下步骤：在硅衬底上形成绝缘层，在所述绝缘层上形成接触孔，在所述接触孔中形成选择性硅层，并在所述选择性硅层上形成选择性导电插塞 。

公开(公告)号：US20130128660A1

公开(公告)日：2013-05-23

申请号：US13475204

申请日：2012-05-18

申请人： Hyun-Seung YOO ,  Sung-Joo HONG ,  Seiichi ARITOME ,  Seok-Kiu LEE ,  Sung-Kye PARK ,  Gyu-Seog CHO ,  Eun-Seok CHOI ,  Han-Soo JOO

发明人： Hyun-Seung YOO ,  Sung-Joo HONG ,  Seiichi ARITOME ,  Seok-Kiu LEE ,  Sung-Kye PARK ,  Gyu-Seog CHO ,  Eun-Seok CHOI ,  Han-Soo JOO

IPC分类号： G11C16/04 ,  G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3418

摘要： A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

摘要翻译： 一种非易失性存储器件的读取方法，包括分别包括一个浮动栅极和两个控制栅极的多个存储器单元，两个控制栅极分别与浮置栅极的两个交替侧相邻设置，并且两个相邻的存储单元共享一个 所述读取方法包括将读取电压施加到所选择的存储器单元的控制栅极，将第二通过电压施加到与所选择的存储器单元的控制栅极不同的存储单元的控制栅极的替代控制栅极，所述存储器单元从控制栅极开始， 所选择的存储单元，以及施加低于第二通过电压的第一通过电压，以从控制栅极开始的第二选择的存储单元开始，将不同于所选存储单元的控制栅极的存储单元的控制栅极交替 。

公开(公告)号：US07300843B2

公开(公告)日：2007-11-27

申请号：US11160269

申请日：2005-06-16

申请人： Seok Kiu Lee

发明人： Seok Kiu Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of fabricating a flash memory device is disclosed wherein, electrode spacers are formed on sides of self-aligned floating gates having a negative slope. Thus, upon etching of a stack gate after an interlayer dielectric film and a control gate are formed, a stringer of a control gate, which is formed by the negative slope of the self-aligned floating gates, can be prevented. Furthermore, because an isotropic etch process is used to remove element isolation films between the floating gates, the element isolation films do not remain on the sides of the floating gates. It is thus possible to prevent loss of the coupling ratio. Accordingly, failure of devices can be reduced and decreasing the program speed can be prevented.

摘要翻译： 公开了一种制造闪存器件的方法，其中电极间隔件形成在具有负斜率的自对准浮动栅极的侧面上。 因此，在层间绝缘膜和控制栅极形成之后蚀刻堆叠栅极时，可以防止由自对准浮动栅极的负斜率形成的控制栅极的纵梁。 此外，由于使用各向同性蚀刻工艺来去除浮置栅极之间的元件隔离膜，元件隔离膜不会残留在浮动栅极的侧面。 因此可以防止耦合比的损失。 因此，可以降低装置的故障，并且可以防止程序速度的降低。

公开(公告)号：US08675404B2

公开(公告)日：2014-03-18

申请号：US13475204

申请日：2012-05-18

申请人： Hyun-Seung Yoo ,  Sung-Joo Hong ,  Seiichi Aritome ,  Seok-Kiu Lee ,  Sung-Kye Park ,  Gyu-Seog Cho ,  Eun-Seok Choi ,  Han-Soo Joo

发明人： Hyun-Seung Yoo ,  Sung-Joo Hong ,  Seiichi Aritome ,  Seok-Kiu Lee ,  Sung-Kye Park ,  Gyu-Seog Cho ,  Eun-Seok Choi ,  Han-Soo Joo

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3418

摘要： A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

摘要翻译： 一种非易失性存储器件的读取方法，包括分别包括一个浮动栅极和两个控制栅极的多个存储器单元，两个控制栅极分别与浮置栅极的两个交替侧相邻设置，并且两个相邻的存储单元共享一个 所述读取方法包括将读取电压施加到所选择的存储器单元的控制栅极，将第二通过电压施加到与所选择的存储器单元的控制栅极不同的存储单元的控制栅极的替代控制栅极，所述存储器单元从控制栅极开始， 所选择的存储单元，以及施加低于第二通过电压的第一通过电压，以从控制栅极开始的第二选择的存储单元开始，将不同于所选存储单元的控制栅极的存储单元的控制栅极交替 。