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    Path status monitoring method and device
    1.
    发明授权
    Path status monitoring method and device 有权
    路径状态监控方法和设备

    公开(公告)号：US07830808B2

    公开(公告)日：2010-11-09

    申请号：US12005608

    申请日：2007-12-28

    申请人： Osamu Takeuchi ,  Yoshitaka Taki ,  Satoru Saitoh ,  Hiroyuki Honma ,  Tomoyoshi Fujimori

    发明人： Osamu Takeuchi ,  Yoshitaka Taki ,  Satoru Saitoh ,  Hiroyuki Honma ,  Tomoyoshi Fujimori

    IPC分类号： G01R31/08

    CPC分类号： H04J3/085

    摘要： In a path status monitoring method and device which can enhance or reduce a band more rapidly, for example, SONET frames FR serially connected over 32 frames to which frame Nos. FN (“0”-“31”)) are assigned are cyclically generated respectively for paths P0-P2 in a cycle TC (=64 ms). After output timing delays TD0-TD2 of the frames FR are shifted by an optimal delay interval D (=21 ms) between the paths P0-P2 based on the number of the paths “3”, the output timing delays TD1 and TD2 are restored by preliminarily obtained transmission delays for the paths P1 and P2 to the path P0. When the frames FR are transmitted through each of the paths P0-P2, statuses (path statuses MST) where a reception fault has occurred in each of the paths P0-P2 are collected to be stored in the frame whose frame No. FN=“0”.

    摘要翻译： 在可以更快速地增强或减少频带的路径状态监视方法和装置中，例如，循环地生成分配了帧号FN（“0”〜“31”）的32帧的串行连接的SONET帧FR 分别用于循环TC（= 64ms）中的路径P0-P2。 在帧FR的输出定时延迟TD0-TD2之后，基于路径“3”的数量，在路径P0-P2之间移动最佳延迟间隔D（= 21ms），恢复输出定时延迟TD1和TD2 通过预先获得路径P1和P2到路径P0的传输延迟。 当通过路径P0-P2中的每一个发送帧FR时，收集在每个路径P0-P2中发生接收故障的状态（路径状态MST）以存储在帧号FN =“ 0“。

    Path status monitoring method and device
    2.
    发明申请
    Path status monitoring method and device 有权
    路径状态监控方法和设备

    公开(公告)号：US20080159156A1

    公开(公告)日：2008-07-03

    申请号：US12005608

    申请日：2007-12-28

    申请人： Osamu Takeuchi ,  Yoshitaka Taki ,  Satoru Saitoh ,  Hiroyuki Honma ,  Tomoyoshi Fujimori

    发明人： Osamu Takeuchi ,  Yoshitaka Taki ,  Satoru Saitoh ,  Hiroyuki Honma ,  Tomoyoshi Fujimori

    IPC分类号： G06F11/00

    CPC分类号： H04J3/085

    摘要： In a path status monitoring method and device which can enhance or reduce a band more rapidly, for example, SONET frames FR serially connected over 32 frames to which frame Nos. FN (“0”-“31”)) are assigned are cyclically generated respectively for paths P0-P2 in a cycle TC (=64 ms). After output timing delays TD0-TD2 of the frames FR are shifted by an optimal delay interval D (=21 ms) between the paths P0-P2 based on the number of the paths “3”, the output timing delays TD1 and TD2 are restored by preliminarily obtained transmission delays for the paths P1 and P2 to the path P0. When the frames FR are transmitted through each of the paths P0-P2, statuses (path statuses MST) where a reception fault has occurred in each of the paths P0-P2 are collected to be stored in the frame whose frame No. FN=“0”.

    摘要翻译： 在可以更快速地增强或减少频带的路径状态监视方法和装置中，例如，循环地生成分配了帧号FN（“0”〜“31”）的32帧的串行连接的SONET帧FR 分别用于循环T C C（= 64ms）中的路径P 0 -P 2。 在帧FR的输出定时延迟之后，在路径P 0 -P 2之间移动最佳延迟间隔D（= 21ms） 基于路径“3”的数量，通过预先获得的路径P 1和P的传输延迟来恢复输出定时延迟T 1 D 2和T 2 D 当通过路径P 0 -P 2中的每一个发送帧FR时，将各路径P 0 -P 2中发生接收故障的状态（路径状态MST）收集为 存储在帧号FN =“0”的帧中。

    Bandwidth controlling method and node apparatus for a ring-based network
    4.
    发明申请
    Bandwidth controlling method and node apparatus for a ring-based network 失效
    用于环网的带宽控制方法和节点装置

    公开(公告)号：US20070070923A1

    公开(公告)日：2007-03-29

    申请号：US11330066

    申请日：2006-01-12

    申请人： Hiroyuki Honma ,  Satoru Saitoh

    发明人： Hiroyuki Honma ,  Satoru Saitoh

    IPC分类号： H04L12/28

    CPC分类号： H04L47/762 ,  H04L47/13 ,  H04L47/70 ,  H04L47/746 ,  H04L47/829

    摘要： The present invention discloses a method for controlling a physical bandwidth of a ring-based network by employing a ring application of a data link layer that operates in a physical layer. The method includes the steps of a) requesting each of a plurality of node apparatuses included in the ring-based network to confirm whether the bandwidth can be changed, b) instructing each node of the apparatuses to prepare for the bandwidth change upon receiving a confirmation that the bandwidth can be changed, c) reporting that the preparation for the bandwidth change is completed, and d) changing the bandwidth by using a bandwidth changing function of the ring application upon receiving the report of the completion of the preparation for the bandwidth change.

    摘要翻译： 本发明公开了一种通过采用在物理层中操作的数据链路层的环应用来控制环网的物理带宽的方法。 该方法包括以下步骤：a）请求包括在基于环的网络中的多个节点装置中的每一个以确认带宽是否可以改变，b）指示装置的每个节点在接收到确认后准备带宽改变 可以改变带宽，c）报告带宽改变的准备工作已经完成，以及d）在接收到完成带宽改变准备工作的报告时，通过使用环应用的带宽改变功能来改变带宽 。

    Semiconductor integrated circuit including command decoder for receiving control signals
    5.
    发明授权
    Semiconductor integrated circuit including command decoder for receiving control signals 有权
    包括用于接收控制信号的命令解码器的半导体集成电路

    公开(公告)号：US06630850B2

    公开(公告)日：2003-10-07

    申请号：US09538721

    申请日：2000-03-30

    申请人： Satoshi Eto ,  Satoru Saitoh ,  Shinichi Yamada

    发明人： Satoshi Eto ,  Satoru Saitoh ,  Shinichi Yamada

    IPC分类号： H03L700

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1087

    摘要： A delay circuit and a plurality of accepting circuits are comprised. The input signal supplied from exterior is delayed for a predetermined length of time by the delay circuit, and then it is distributed and output to the plurality of the receiver circuits. The delay time of the delay circuit is adjusted to optimize an accepting timing to an input signal by a clock signal in each of the accepting circuit. The each accepting circuit reliably accepts the delayed input signal respectively in synchronization with a clock signal. Therefore, it is unnecessary to respectively provide a delay circuit in the plurality of the accepting circuits. As a result, the plurality of accepting circuits can reliably accept input signals without enlarging a circuit scale. A plurality of delay circuits, a plurality of accepting circuits, and an operating circuit are comprised. The delay circuit receives a plurality of input signals, and outputs each of the delayed input signals respectively to the plurality of accepting circuits. The accepting circuit accepts the delayed input signals in synchronization with a clock signal. More than one of the delayed input signals are supplied to the operating circuit to perform a logic operation. The delay time of the each delay circuit, for example, is in accordance with the supplying timing to the input signal supplied to the operating circuit. As a result, the operating circuit performs the logic operation with a sufficient timing margin.

    摘要翻译： 包括延迟电路和多个接受电路。 由外部提供的输入信号由延迟电路延迟预定的时间长度，然后被分配并输出到多个接收器电路。 调整延迟电路的延迟时间，以通过每个接收电路中的时钟信号来优化对输入信号的接受定时。 每个接收电路可以与时钟信号同步地可靠地接受延迟的输入信号。 因此，不需要在多个接受电路中分别提供延迟电路。 结果，多个接受电路可以可靠地接受输入信号而不放大电路规模。 包括多个延迟电路，多个接受电路和操作电路。 延迟电路接收多个输入信号，并且分别将多个延迟输入信号输出到多个接受电路。 接受电路与时钟信号同步地接受延迟的输入信号。 多个延迟的输入信号被提供给操作电路以执行逻辑操作。 例如，每个延迟电路的延迟时间与提供给操作电路的输入信号的提供时序相一致。 结果，操作电路以足够的定时裕度执行逻辑运算。

    BRAZING FLUX POWDER FOR ALUMINUM-BASED MATERIAL AND PRODUCTION METHOD OF FLUX POWDER
    7.
    发明申请
    BRAZING FLUX POWDER FOR ALUMINUM-BASED MATERIAL AND PRODUCTION METHOD OF FLUX POWDER 审中-公开
    用于铝基材料的烧结粉末和粉末生产方法

    公开(公告)号：US20090050239A1

    公开(公告)日：2009-02-26

    申请号：US11909480

    申请日：2006-03-23

    申请人： Kazuyoshi Honda ,  Satoru Saitoh

    发明人： Kazuyoshi Honda ,  Satoru Saitoh

    IPC分类号： B23K35/22 ,  B22F9/16

    CPC分类号： B23K35/3605

    摘要： It is aimed at providing a brazing flux powder, which exhibits an excellent spreadability in case of brazing of an Mg-containing aluminum-based material, which is non-corrosive and is thus excellent in safety, which is relatively inexpensive and is thus economically excellent, and which can be used in a wide and general manner. There is provided an improvement in a flux powder containing therein KAlF4, K2AlF5, and K2AlF5·H2O, usable for brazing of an aluminum-based material having an Mg content of 0.1 to 1.0 wt %, and the improving characteristic configuration resides in that the flux powder has a composition where a K/Al molar ratio is within a range of 1.00 to 1.20 and an F/Al molar ratio is within a range of 3.80 to 4.10, and the K2AlF5 and K2AlF5·H2O have a sum content of 6.0 to 40.0 wt %, balance KAlF4, and that part or the whole of the crystal structure of K2AlF5·H2O is at least one of a K-defective type, F-defective type, and K-and-F-defective type crystal structure.

    摘要翻译： 本发明的目的在于提供一种钎焊助焊剂粉末，其在不腐蚀性的Mg含量的铝基材料的钎焊的情况下具有优异的铺展性，因此安全性优异，因此其成本相对便宜，因此经济地优异 ，并且可以以广泛和一般的方式使用。 提供含有KAlF 4，K 2 AlF 5和K 2 AlF 5·H 2 O的焊剂粉末的改进，其可用于Mg含量为0.1至1.0重量％的铝基材料的钎焊，并且改进的特征构造在于助焊剂 粉末具有K / Al摩尔比在1.00〜1.20的范围内且F / Al摩尔比在3.80〜4.10的范围内的组成，K2AlF5和K2AlF5·H2O的总含量为6.0〜40.0 重量％，余量为KAlF4，K2AlF5.H2O的部分或全部晶体结构为K型缺陷型，F型缺陷型，K型和F型缺陷型晶体结构中的至少一种。

    Semiconductor integrated circuit device capable of reading out chip-specific information during testing and evaluation
    9.
    发明授权
    Semiconductor integrated circuit device capable of reading out chip-specific information during testing and evaluation 失效
    半导体集成电路器件能够在测试和评估期间读出芯片特定的信息

    公开(公告)号：US06330297B1

    公开(公告)日：2001-12-11

    申请号：US09515651

    申请日：2000-02-29

    申请人： Hideki Kano ,  Shinichi Yamada ,  Satoru Saitoh

    发明人： Hideki Kano ,  Shinichi Yamada ,  Satoru Saitoh

    IPC分类号： G04F1004

    CPC分类号： G11C29/12 ,  G11C2029/4402

    摘要： A semiconductor integrated circuit device has a data holding section for storing information, a counter for counting the number of externally applied pulses, and a comparison/verification section. The comparison/verification section compares an output of the counter with an output of the data holding section, and verifies whether the outputs match or not. This configuration serves to reduce the number of wiring lines formed from pads to a comparison/verification circuit (a signature circuit), and thereby achieves a reduction in layout area and facilitates efficient layout work.

    摘要翻译： 半导体集成电路装置具有用于存储信息的数据保持部分，用于对外部施加的脉冲数进行计数的计数器以及比较/验证部分。 比较/验证部分将计数器的输出与数据保持部分的输出进行比较，并且验证输出是否匹配。 该配置用于将由焊盘形成的布线的数量减少到比较/验证电路（签名电路），从而实现布局面积的减小并且有利于布局工作的有效性。

    Semiconductor memory device having read/write amplifiers disposed for respective memory segments
    10.
    发明授权
    Semiconductor memory device having read/write amplifiers disposed for respective memory segments 有权
    具有为相应存储器段设置的读/写放大器的半导体存储器件

    公开(公告)号：US06246628B1

    公开(公告)日：2001-06-12

    申请号：US09537384

    申请日：2000-03-29

    申请人： Masatomo Hasegawa ,  Shinichi Yamada ,  Satoru Saitoh

    发明人： Masatomo Hasegawa ,  Shinichi Yamada ,  Satoru Saitoh

    IPC分类号： G11C800

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C8/12

    摘要： Segment selection circuits 40A are arranged adjacent read/write amplifiers 20. When one of the segments 0 to 7 in a memory cell array 10 is selected by a signal on segment address lines CA8 to CA6, a read amplifier 21 or a write amplifier 22 of the read/write amplifier 20 corresponding to the selected segment is activated in response to activation of a signal on a read timing signal line RT or a write timing signal line WT. The lines CA8 to CA6, RT and WT are arranged along the row of the segment selection circuits 40A.

    摘要翻译： 段选择电路40A被布置在读/写放大器20相邻处。当存储单元阵列10中的片段0至7之一被片地址线CA8至CA6上的信号选择时，读放大器21或写放大器22 响应于读定时信号线RT或写定时信号线WT上的信号的激活，激活对应于所选择的段的读/写放大器20。 线CA8至CA6，RT和WT沿着段选择电路40A的行布置。