公开(公告)号：US20130208817A1

公开(公告)日：2013-08-15

申请号：US13397158

申请日：2012-02-15

Applicant: ROBERT C. ELLIOTT

Inventor： ROBERT C. ELLIOTT

IPC: H04L27/00

CPC classification number: H04L25/03343

Abstract: A communication system and method are disclosed. The system includes a receiver to receive and process a transmission signal provided from a transmitter based on a digital input signal, and to generate a receiver signal that indicates eye characteristics associated with transmission characteristics of the processed transmission signal. The transmission characteristics can be set by a digital filter associated with the transmitter based on filter parameters. The system further includes a transmitter training system to implement a plurality of experiments based on implementing Design of Experiments (DOE) to provide the filter parameters to the transmitter and to evaluate the corresponding eye characteristics to determine an output set of filter parameters.

Abstract translation: 公开了一种通信系统和方法。 该系统包括接收器，用于基于数字输入信号接收和处理从发射机提供的传输信号，并产生指示与经处理的传输信号的传输特性相关联的眼睛特性的接收机信号。 可以通过基于滤波器参数的与发射机相关联的数字滤波器来设置传输特性。 该系统还包括发射机训练系统，用于基于实现实验设计（DOE）来实施多个实验，以向发射机提供滤波器参数，并评估相应的眼睛特性以确定滤波器参数的输出集合。

公开(公告)号：US07295513B2

公开(公告)日：2007-11-13

申请号：US10669151

申请日：2003-09-23

Applicant: Robert C. Elliott ,  Witold A. Krzymien

Inventor： Robert C. Elliott ,  Witold A. Krzymien

IPC: G01R31/08 ,  G06F11/00 ,  G08C15/00

CPC classification number: H04W72/1226 ,  H04L12/1881 ,  H04L12/189 ,  H04W72/1247

Abstract: A method for scheduling packet data transmissions in a wireless communication system is described wherein a priority function is based on a channel state indicator (CSI), the projected average throughput of the users, and a tuning parameter designed to control the throughput and fairness characteristics of the scheduling algorithm. The method also considers fairness criteria dictated by predetermined Quality of Service (QoS) requirements. The channel state indicator may be a Requested Data Rate (RDR) or Carrier-to-Interference ratio (C/I) information. The base station calculates a priority function for the multiple mobile users. Each priority function is a function of the CSI, the projected average throughput of a given mobile user, the average projected throughput over a set of users, and the tuning parameter.

Abstract translation: 描述了一种用于在无线通信系统中调度分组数据传输的方法，其中优先级功能基于信道状态指示符（CSI），用户的预计平均吞吐量以及调整参数，该调整参数旨在控制吞吐量和公平性 调度算法。 该方法还考虑了由预定的服务质量（QoS）要求所规定的公平性标准。 信道状态指示符可以是请求数据速率（RDR）或载波干扰比（C / I）信息。 基站计算多个移动用户的优先级功能。 每个优先级功能是CSI的功能，给定移动用户的预计平均吞吐量，一组用户的平均预计吞吐量以及调谐参数。

公开(公告)号：US06070215A

公开(公告)日：2000-05-30

申请号：US42326

申请日：1998-03-13

Applicant: Todd J. Deschepper ,  Robert C. Elliott

Inventor： Todd J. Deschepper ,  Robert C. Elliott

IPC: G06F1/32 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F1/3203 ,  G06F13/4031

Abstract: A computer system includes a South bridge logic device that monitors the FLUSHREQ signal and masks that signal when the CPU transitions the computer to a low power mode of operation. Once masked, the FLUSHREQ cannot be asserted to the North bridge and the conflict between attempts by the CPU and an ISA device to run cycles on the PCI bus is avoided. The South bridge also masks all requests to run cycles on the PCI bus that are not originated by the CPU. The South bridge includes a programmable control register and a PCI arbiter. When a control bit is set in the register, the PCI arbiter waits for FLUSHREQ to be deasserted and then masks FLUSHREQ. The PCI arbiter preferably also disables PCI arbitration by masking all non-CPU. Only the CPU can run PCI cycles when the non-CPU requests are masked. The programmable control register also includes a masking status bit that is set when both the FLUSHREQ and non-CPU request signals are masked by a request mask state machine. The computer system may also include a laptop computer docked to an expansion base with a South bridge included in the computer and the expansion base.

Abstract translation: 计算机系统包括南桥逻辑器件，其监视FLUSHREQ信号和当CPU将计算机转换到低功耗操作模式时信号的掩码。 一旦屏蔽，FLUSHREQ不能被断言到北桥，并且避免CPU和ISA设备在PCI总线上运行周期的冲突。 南桥还屏蔽了PCI总线上运行不是由CPU发起的周期的所有请求。 南桥包括一个可编程控制寄存器和一个PCI仲裁器。 当寄存器中设置了一个控制位时，PCI仲裁器等待FLUSHREQ被取消置位，然后屏蔽FLUSHREQ。 PCI仲裁器也优选地通过屏蔽所有非CPU来禁用PCI仲裁。 当非CPU请求被屏蔽时，只有CPU可以运行PCI周期。 可编程控制寄存器还包括当FLUSHREQ和非CPU请求信号被请求掩码状态机屏蔽时设置的屏蔽状态位。 计算机系统还可以包括与包括在计算机中的南桥和扩展基座对接的扩展基座的膝上型计算机。

公开(公告)号：US5999198A

公开(公告)日：1999-12-07

申请号：US925772

申请日：1997-09-09

Applicant: Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

Inventor： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

IPC: G06F3/14 ,  G06F12/08 ,  G09G5/393 ,  G06F15/16

CPC classification number: G06F3/14 ,  G06F12/0875 ,  G09G5/393 ,  G09G2360/121

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Abstract translation: 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器页面的基址的地址指针，以及可用于定制关联的存储器页面的特征标志。

公开(公告)号：US5539386A

公开(公告)日：1996-07-23

申请号：US206972

申请日：1994-03-07

Applicant: Robert C. Elliott

Inventor： Robert C. Elliott

IPC: G01N21/41 ,  G08B17/103

CPC classification number: G01N21/41 ,  Y10S128/13

Abstract: A non-intrusive optical transmission liquid monitoring system that detects bubbles in a transparent liquid flowing through a transparent tubing. The system dynamically compensates for changes in optical transmission efficiency of the monitored liquid and distinguishes between the transition from liquid to air and air to liquid. A system comprising a light transmitter and a light sensitive receiver secured on opposite sides of a transparent tubing. The output of the receiver is fed into a self-referencing and drift compensation circuit. The integrated output is connected to circuitry sensitive to a change in the integrated output and triggers one of two possible alarms to indicate a detected transition from liquid to air, or air to liquid.

Abstract translation: 一种非侵入式透光液体监测系统，用于检测流过透明管道的透明液体中的气泡。 系统动态地补偿被监测液体的光传输效率的变化，并区分从液体到空气和空气到液体的过渡。 一种包括光传输器和固定在透明管道的相对侧上的光敏接收器的系统。 接收机的输出馈入自参考和漂移补偿电路。 集成输出连接到对集成输出变化敏感的电路，并触发两个可能的报警之一，以指示从液体到空气或空气到液体的检测过渡。

公开(公告)号：US08417967B2

公开(公告)日：2013-04-09

申请号：US12935715

申请日：2008-04-02

Applicant: Joseph E. Foster ,  Robert C. Elliott ,  Jeffrey A. Plank

Inventor： Joseph E. Foster ,  Robert C. Elliott ,  Jeffrey A. Plank

IPC: G06F11/30 ,  G06F12/14 ,  H04K1/00 ,  H04L9/00 ,  H04L9/30

CPC classification number: H04L63/06 ,  G06F21/78 ,  G06F2221/2107 ,  G11B20/0021 ,  G11B2220/415

Abstract: Embodiments include methods, apparatus, and systems for storage device data encryption. One method includes encrypting data on a storage device with a key and then transmitting the key to a cryptographic module that encrypts the key to form a Binary Large Object (BLOB). The BLOB is transmitted to an array controller that is coupled to the storage device which stores the BLOB.

Abstract translation: 实施例包括用于存储设备数据加密的方法，设备和系统。 一种方法包括使用密钥对存储设备上的数据进行加密，然后将密钥发送到加密密钥以形成二进制大对象（BLOB）的加密模块。 BLOB被发送到阵列控制器，该阵列控制器耦合到存储该BLOB的存储设备。

公开(公告)号：US07644168B2

公开(公告)日：2010-01-05

申请号：US11180145

申请日：2005-07-13

Applicant: Thomas W. Grieff ,  Robert C. Elliott

Inventor： Thomas W. Grieff ,  Robert C. Elliott

IPC: G06F15/16 ,  G06F3/00

CPC classification number: G06F13/387

Abstract: Systems and methodologies associated with providing additional functionality to a conventional SAS expander are described. One exemplary SAS expander embodiment includes logic for selectively performing source identifier checking for frames received at the SAS expander. The logic may also facilitate selectively performing explicit route checking for frames received at the SAS expander. In one example, the logic may also facilitate selectively providing VLAN-like services to devices connected to the SAS expander.

Abstract translation: 描述了与常规SAS扩展器提供附加功能相关联的系统和方法。 一个示例性的SAS扩展器实施例包括用于选择性地执行在SAS扩展器处接收的帧的源标识符检查的逻辑。 逻辑还可以有助于选择性地执行在SAS扩展器处接收到的帧的显式路由检查。 在一个示例中，逻辑还可以有助于选择性地向连接到SAS扩展器的设备提供类VLAN的服务。

公开(公告)号：US07028106B2

公开(公告)日：2006-04-11

申请号：US10728480

申请日：2003-12-05

Applicant: Joseph E. Foster ,  Robert C. Elliott ,  Hubert E. Brinkmann, Jr. ,  James R. Reif

Inventor： Joseph E. Foster ,  Robert C. Elliott ,  Hubert E. Brinkmann, Jr. ,  James R. Reif

IPC: G06F13/00

CPC classification number: G06F13/404 ,  G06F13/4045

Abstract: A system includes a peripheral device and an expander having interfaces to couple to one or more peripheral devices and an expander. The expander has a storage to store entries containing routing information used to route a request received by the expander to one of the interfaces, wherein each interface is allocated to a respective set of routing information entries. Mapping logic remaps unused routing information of one of the interfaces to one or more other interfaces to expand capacity of the one or more other interfaces.

Abstract translation: 一种系统包括具有耦合到一个或多个外围设备和扩展器的接口的外围设备和扩展器。 扩展器具有存储，用于存储包含用于将扩展器接收的请求路由到其中一个接口的路由信息​​的条目，其中每个接口被分配给相应的一组路由信息条目。 映射逻辑将其中一个接口的未使用路由信息重新映射到一个或多个其他接口，以扩展一个或多个其他接口的容量。

公开(公告)号：US06546497B1

公开(公告)日：2003-04-08

申请号：US09507072

申请日：2000-02-18

Applicant: William C. Galloway ,  Robert C. Elliott

Inventor： William C. Galloway ,  Robert C. Elliott

IPC: G06F104

CPC classification number: G06F13/4045

Abstract: A SCSI initiator, repeater, or device is provided that stretches an initial assertion of the REQ# or ACK# clock signals on the SCSI bus after a period of inactivity on the SCSI data lines. This discharges built up charge allowing greater signal integrity on ensuing clocks.

Abstract translation: 提供了一个SCSI启动器，中继器或者设备，它在SCSI数据线上一段时间不活动之后，延长SCSI总线上的REQ＃或ACK＃时钟信号的初始断言。 这样可以释放建立的电荷，从而在随后的时钟上实现更高的信号完整性。

公开(公告)号：US06279087B1

公开(公告)日：2001-08-21

申请号：US08995945

申请日：1997-12-22

Applicant: Maria L. Melo ,  Khaldoun Alzien ,  Robert C. Elliott ,  David J. Maguire

Inventor： Maria L. Melo ,  Khaldoun Alzien ,  Robert C. Elliott ,  David J. Maguire

IPC: G06F1216

CPC classification number: G06F13/4036 ,  G06F12/0835

Abstract: A bridge logic unit provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to memory bus, and a peripheral device coupled to a peripheral bus, such as a PCI bus. To maintain coherency, the bridge logic unit disables write posting in certain specific situations, and flushes posted write transactions before allowing certain read requests to be serviced. More specifically, in one embodiment when a PCI device performs a read to main memory, which may be implemented within the bridge as delayed read, the bus bridge blocks CPU to PCI transactions and flushes any posted CPU to PCI transactions pending in the bridge. The bus bridge enables CPU to PCI posting after the pending CPU to PCI transactions have been flushed and after the snoop phase of a snoop cycle corresponding to the memory read operation completes. In a further embodiment, prior to performing a PCI read cycle on behalf of a read cycle initiated by the microprocessor, the bus bridge determines whether any PCI to memory transactions are pending in the PCI slave transient write buffer. If any posted write transactions reside in the PCI slave transient write buffer, the bus bridge retries the read cycle on the processor bus and blocks any subsequent posting of write transactions to memory from the PCI bus. When the pending PCI to memory transactions have been flushed from the PCI slave transient write buffer, and the microprocessor reattempts the read, the read cycle is initiated on the PCI bus. At this point, PCI to memory write posting is re-enabled.

Abstract translation: 桥逻辑单元提供耦合到处理器总线的微处理器，耦合到存储器总线的主存储器和耦合到诸如PCI总线的外围总线的外围设备之间的接口。 为了保持一致性，桥逻辑单元在某些特定情况下禁用写入过帐，并在允许某些读请求被服务之前刷新已发布的写事务。 更具体地说，在一个实施例中，当PCI设备执行对主存储器的读取（其可以在桥接器内实现为延迟读取）时，总线桥接器阻塞CPU到PCI事务，并将任何已发布的CPU刷新到桥中待处理的PCI事务。 在挂起的CPU到PCI事务被刷新之后，以及在与存储器读操作相对应的窥探周期的窥探阶段完成之后，总线桥使CPU到PCI发布。 在另一个实施例中，在代表由微处理器发起的读周期执行PCI读周期之前，总线桥确定PCI从瞬态写缓冲器中是否有任何PCI到存储器事务挂起。 如果任何已发布的写入事务驻留在PCI从属瞬态写入缓冲区中，则总线桥重试处理器总线上的读取周期，并阻止从PCI总线向存储器发送写入事务的任何后续过程。 当待机PCI到内存事务已经从PCI从站瞬态写入缓冲器中刷新，并且微处理器重新尝试读取时，读取周期将在PCI总线上启动。 此时，重新启用PCI到内存写入过帐。