公开(公告)号：US5991833A

公开(公告)日：1999-11-23

申请号：US42036

申请日：1998-03-13

申请人： Shaun V. Wandler ,  Maria L. Melo ,  Todd Deschepper

发明人： Shaun V. Wandler ,  Maria L. Melo ,  Todd Deschepper

IPC分类号： G06F13/40 ,  G06F13/38

CPC分类号： G06F13/4027

摘要： A computer system includes a CPU and a memory device coupled through a North bridge logic device. The computer also includes a South bridge logic device coupled to the North bridge by a primary bus. The South bridge waits as long as possible before asserting a flush request (FLUSHREQ) control signal to the North bridge. The South bridge asserts the FLUSHREQ signal to the North bridge after a peripheral device coupled to the South bridge requests access to the primary bus to run a cycle. The South bridge first flushes a write queue before asserting the FLUSHREQ signal to the North bridge. In response to the FLUSHREQ control signal, the North bridge flushes one or more of its own internal write queues in preparation for the upcoming peripheral device cycle. By flushing its own internal write queue before asserting FLUSHREQ to the North bridge, the South bridge reduces the amount of time that the CPU will be prevented from accessing the primary expansion bus while the peripheral device attempts to run a cycle on the primary bus. An alternative embodiment of the invention includes a pair of South bridges, one South bridge in a laptop computer and the other South bridge in an expansion base to which the laptop computer mates.

摘要翻译： 计算机系统包括CPU和通过北桥逻辑器件耦合的存储器件。 计算机还包括通过主总线耦合到北桥的南桥逻辑设备。 在向北桥发出刷新请求（FLUSHREQ）控制信号之前，南桥等待尽可能长的时间。 南桥在连接到南桥后的外围设备请求访问主总线运行一个周期时，向北桥断言FLUSHREQ信号。 南桥首先刷新一个写队列，然后再向北桥发出FLUSHREQ信号。 响应于FLUSHREQ控制信号，北桥冲洗一个或多个自己的内部写队列，以准备即将到来的外围设备周期。 在将FLUSHREQ置于北桥之前，通过刷新自己的内部写入队列，南桥可以减少在外围设备尝试在主总线上运行一个周期时CPU将被阻止访问主扩展总线的时间。 本发明的替代实施例包括一对南桥，笔记本电脑中的一个南桥，以及膝上型计算机与之相配合的扩展基座中的另一南桥。

公开(公告)号：US5987555A

公开(公告)日：1999-11-16

申请号：US995386

申请日：1997-12-22

申请人： Khaldoun Alzien ,  Maria L. Melo ,  Todd J. DeSchepper

发明人： Khaldoun Alzien ,  Maria L. Melo ,  Todd J. DeSchepper

IPC分类号： G06F13/40 ,  G06F13/00 ,  G06F13/20

CPC分类号： G06F13/4031

摘要： A PCI bridge is configured to perform delayed read operations in response to a memory read initiated on the PCI bus. Normally, the PCI bridge is configured to discard delayed read data read from main memory following a predetermined discard count time after the PCI master establishing the delayed read operation is retried on the PCI bus. The computer system further includes a secondary bus bridge such as an ISA bridge for providing an interface between the PCI bus and an ISA bus. When an ISA device desires to read data from the main memory, the ISA bridge asserts a flush request signal. The PCI bridge responsively flushes any pending CPU to PCI transactions pending within the PCI bridge. When the flushing operation is complete, the PCI bridge asserts an acknowledge signal. A PCI arbiter for arbitrating ownership of the PCI bus may increase a level of arbitration priority provided to the ISA bridge in response to assertion of the acknowledge signal. The PCI bridge is advantageously configured to decrease the time associated with discarding of the delayed read data when the acknowledge signal is asserted.

摘要翻译： PCI桥被配置为响应于在PCI总线上发起的存储器读取而执行延迟读取操作。 通常，PCI桥被配置为在PCI主机建立延迟读取操作在PCI总线上重试之后的预定丢弃计数时间之后丢弃从主存储器读取的延迟读取数据。 计算机系统还包括辅助总线桥，例如ISA桥，用于提供PCI总线和ISA总线之间的接口。 当ISA设备希望从主存储器读取数据时，ISA桥断言刷新请求信号。 PCI桥接器响应性地将任何待处理的CPU刷新到PCI桥内待处理的PCI事务。 当冲洗操作完成时，PCI桥断言一个确认信号。 用于仲裁PCI总线的所有权的PCI仲裁器可以响应于确认信号的断言而增加提供给ISA桥的仲裁优先级。 有利地，PCI桥被配置为当确认确认信号被断言时，减少与丢弃延迟的读取数据相关联的时间。

公开(公告)号：US5867728A

公开(公告)日：1999-02-02

申请号：US768308

申请日：1996-12-17

申请人： Maria L. Melo ,  James R. Reif

发明人： Maria L. Melo ,  James R. Reif

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027

摘要： To assure that memory and/or I/O cycles will run correctly after a PCI device configuration cycle that changes memory and/or I/O mapping, in a multi-processor P6 computer system that pipelines instructions. The memory and I/O cycles are suspended on the processor bus until the configuration cycle has been completed. A signal is generated within the address decode logic to prevent address decoding from taking place if a PCI device is being configured. During the configuration transactions, other pipelined transaction cycles are snoop stalled until the PCI configuration write has been completed.

摘要翻译： 为了确保内存和/或I / O周期在更改内存和/或I / O映射的PCI设备配置周期后能够在管理指令的多处理器P6计算机系统中正常运行。 存储器和I / O周期暂停在处理器总线上，直到配置周期完成。 在地址解码逻辑中产生信号，以防止在配置PCI设备时发生地址解码。 在配置事务期间，其他流水线事务周期被窥探停止，直到PCI配置写入完成。

公开(公告)号：US5553310A

公开(公告)日：1996-09-03

申请号：US955930

申请日：1992-10-02

申请人： Mark Taylor ,  Paul R. Culley ,  Maria L. Melo ,  Roger E. Tipley

发明人： Mark Taylor ,  Paul R. Culley ,  Maria L. Melo ,  Roger E. Tipley

IPC分类号： G06F13/364 ,  G06F13/14 ,  G06F13/18

CPC分类号： G06F13/364

摘要： Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

摘要翻译： 用于确定几个CPU中的哪一个接收优先级以在多处理器系统中成为主机总线的总线主机的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制传输何时由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 分割事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被另一个设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：US06243817B1

公开(公告)日：2001-06-05

申请号：US08995703

申请日：1997-12-22

申请人： Maria L. Melo ,  James R. Reif ,  David J. Maguire

发明人： Maria L. Melo ,  James R. Reif ,  David J. Maguire

IPC分类号： G06F126

CPC分类号： G06F1/3253 ,  G06F1/3203 ,  Y02D10/151

摘要： A computer is provided having a bus interface unit coupled between a CPU bus and a mezzanine bus, or PCI bus. The bus interface unit includes a plurality of input buffers which can be selectively connected and disconnected in a dynamic fashion according to active and inactive signals forwarded thereto. Signals forwarded to the bus interface unit from the CPU are classified according to the transaction phase of CPU bus activity. If signals associated with one particular transaction phase are active, then input buffers attributed to signals of other transaction phases can be deactivated. It is preferred that input buffers associated with signals of a request and arbitration phase be maintained active and coupled to power regardless of the present transaction phase unless the computer enters a powered down mode, such as sleep, idle or standby.

摘要翻译： 提供了一种具有耦合在CPU总线和夹层总线或PCI总线之间的总线接口单元的计算机。 总线接口单元包括多个输入缓冲器，其可以根据转发给其的有源和非活动信号以动态方式选择性地连接和断开。 根据CPU总线活动的事务阶段对从CPU传送到总线接口单元的信号进行分类。 如果与一个特定事务阶段相关联的信号是有效的，则归因于其他事务阶段的信号的输入缓冲器可以被去激活。 优选的是，与请求和仲裁阶段的信号相关联的输入缓冲器保持有效并且与当前事务阶段无关地耦合到功率，除非计算机进入诸如睡眠，空闲或待机的断电模式。

公开(公告)号：US6040845A

公开(公告)日：2000-03-21

申请号：US995763

申请日：1997-12-22

申请人： Maria L. Melo ,  Gregory N. Santos

发明人： Maria L. Melo ,  Gregory N. Santos

IPC分类号： G06F1/32 ,  G06F13/364 ,  G06F13/14

CPC分类号： G06F1/3253 ,  G06F1/3203 ,  G06F13/364 ,  Y02B60/1235 ,  Y02B60/32

摘要： A computer is provided having a bus interface unit which is coupled between a peripheral bus and a dedicated graphics bus. The graphics bus can be linked to the bus interface unit by an AGP, while the peripheral bus can be linked to the bus interface unit by a PCI. Arbitration for the AGP bus can determine when mastership is granted to an AGP master (i.e., graphics accelerator/controller). Until mastership is granted, the AGP target is powered down to a low power state where power consumption within the bus interface unit is minimal. It is not until the AGP master achieves mastership that the graphics target (core logic and memory controller) within the bus interface unit is placed in an operational (fully powered) state. The computer therefore employs a bus interface unit which can be dynamically switched from a high power state to a low power state and vice versa, depending upon accesses to the graphics target.

摘要翻译： 提供一种计算机，其具有耦合在外围总线和专用图形总线之间的总线接口单元。 图形总线可以通过AGP链接到总线接口单元，而外设总线可以通过PCI链接到总线接口单元。 AGP总线的仲裁可以确定何时授予AGP主控（即图形加速器/控制器）。 在授予主管权之前，AGP目标将降低到总线接口单元内的功耗最小的低功耗状态。 直到AGP主机达到掌握，总线接口单元内的图形目标（核心逻辑和存储器控制器）才能处于运行状态（完全供电）状态。 因此，计算机采用总线接口单元，其可以根据对图形目标的访问而从高功率状态动态切换到低功率状态，反之亦然。

公开(公告)号：US5797020A

公开(公告)日：1998-08-18

申请号：US692207

申请日：1996-08-05

申请人： Randy M. Bonella ,  Maria L. Melo

发明人： Randy M. Bonella ,  Maria L. Melo

IPC分类号： G06F13/362 ,  G06F13/364 ,  G06F13/14

CPC分类号： G06F13/364

摘要： An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

公开(公告)号：US06199131B1

公开(公告)日：2001-03-06

申请号：US08995699

申请日：1997-12-22

申请人： Maria L. Melo ,  Khaldoun Alzien ,  Todd J. DeSchepper

发明人： Maria L. Melo ,  Khaldoun Alzien ,  Todd J. DeSchepper

IPC分类号： G06F1300

CPC分类号： G06F13/362 ,  G06F13/4031

摘要： A computer system includes a bus bridge which provides an interface between a main memory and a peripheral bus such as a PCI bus. A peripheral bus interface unit is provided which supports delayed transactions. When a PCI bus master effectuates a read cycle to read data from main memory on the PCI bus, the peripheral bus interface detects the read cycle and terminates or retries the transaction on the PCI bus. The peripheral bus interface further requests the read data from main memory and places the read data in a buffer. When the PCI master device re-attempts the read transaction, the peripheral interface provides the read data directly from its delayed read buffer. When the peripheral bus interface retries the PCI master that establishes a delayed read operation, the peripheral bus interface asserts a control signal referred to the delayed cycle signal. A PCI arbiter which controls ownership of the PCI bus receives the delayed cycle signal and, in response to its assertion, lowers a level of arbitration priority provided to the PCI master establishing the delayed read. In one embodiment, the PCI arbiter inhibits ownership of the PCI bus by the master establishing the delayed read in response to assertion of the delayed cycle signal. When the peripheral bus interface receives the read data and is ready to deliver it to the PCI bus, the delayed cycle signal is deasserted (or strobed). The PCI bus arbiter detects this deassertion (or strobing) of the delayed cycle signal and responsively raises a level of arbitration priority to the PCI master establishing the delayed read. In one implementation, upon detecting the deassertion of the delayed cycle signal, the PCI bus arbiter provides a highest level of arbitration priority to the PCI master establishing the delayed read. The delayed read operation then completes when the PCI master re-initiates the read cycle. The optimized arbitration technique may similarly be employed during other delayed transactions, such as memory writes, I/O read or writes, and configuration reads or writes.

公开(公告)号：US5553248A

公开(公告)日：1996-09-03

申请号：US956034

申请日：1992-10-02

申请人： Maria L. Melo ,  Jeff W. Wolford ,  Michael Moriarty ,  Paul R. Culley ,  Arnold T. Schnell

发明人： Maria L. Melo ,  Jeff W. Wolford ,  Michael Moriarty ,  Paul R. Culley ,  Arnold T. Schnell

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F15/16 ,  G06F15/177 ,  G06F13/20 ,  G06F13/26

CPC分类号： G06F13/36 ,  G06F13/362

摘要： Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

摘要翻译： 用于确定几个CPU中的哪一个接收优先级以在多处理器系统中成为主机总线的总线主机的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制传输何时由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 分割事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被另一个设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：US06212590B1

公开(公告)日：2001-04-03

申请号：US09042038

申请日：1998-03-13

申请人： Maria L. Melo ,  Todd Deschepper ,  Jeffrey T. Wilson

发明人： Maria L. Melo ,  Todd Deschepper ,  Jeffrey T. Wilson

IPC分类号： G06F1336

CPC分类号： G06F13/362 ,  G06F13/4031

摘要： A computer system includes a secondary bus bridge device in a portable computer and a another secondary bus bridge device in an expansion base to which the portable computer connects (docks). A peripheral in the expansion base may initiate a delayed cycle to read or write data to memory through a primary bus bridge device that also couples to a CPU. Both secondary bus bridge devices include an arbiter for controlling arbitration of a peripheral bus that connects both secondary bridge devices. The arbiter in the secondary bridge of the portable computer determines which of the arbiters will have arbitration control of the expansion bus to run cycles. When read data is available, in the case of a delayed read cycle initiated by a peripheral device in the expansion base, the primary bridge strobes a delayed cycle control signal to the arbiter in the portable computer which then gives arbitration control to the arbiter in the expansion base.

摘要翻译： 计算机系统包括便携式计算机中的辅助总线桥接器件以及便携式计算机连接（扩展坞）的扩展基座中的另一辅助总线桥接器件。 扩展基站中的外围设备可能会启动延迟周期，以便通过也耦合到CPU的主总线桥接器件将数据读取或写入存储器。 辅助总线桥接器件包括用于控制连接两个次级桥接器件的外围总线仲裁的仲裁器。 便携式计算机的次级桥中的仲裁器确定哪个仲裁者将对扩展总线进行仲裁控制以运行周期。 当读取数据可用时，在由扩展基站中的外围设备发起的延迟读周期的情况下，主桥选择延迟的周期控制信号给便携式计算机中的仲裁器，然后仲裁器向仲裁器提供仲裁控制 扩建基地