公开(公告)号：US06452830B2

公开(公告)日：2002-09-17

申请号：US09767805

申请日：2001-01-22

申请人： Oskar Kowarik ,  Kurt Hoffmann

发明人： Oskar Kowarik ,  Kurt Hoffmann

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A memory configuration includes a plurality of resistive ferroelectric memory cells. Each of the memory cells includes a selection transistor and a storage capacitor. The selection transistor has a given zone of a first conductivity type. The storage capacitor has a first and a second electrode. The first electrode is supplied with a fixed cell plate voltage, the second electrode is connected to the given zone of the first conductivity type. A source and a drain of a MOS transistor are supplied with the fixed cell plate voltage. The channel of the MOS transistor has a channel length extending over at least two of the memory cells. The given zone of the first conductivity type is connected, via a resistor, to the channel of the MOS transistor such that the given zone is electrically connected to the first electrode of the storage capacitor via the resistor and the MOS transistor.

摘要翻译： 存储器配置包括多个电阻式铁电存储单元。 每个存储单元包括选择晶体管和存储电容器。 选择晶体管具有第一导电类型的给定区域。 存储电容器具有第一和第二电极。 第一电极被提供有固定电池板电压，第二电极连接到第一导电类型的给定区域。 MOS晶体管的源极和漏极被提供有固定电池板电压。 MOS晶体管的沟道具有在至少两个存储单元上延伸的沟道长度。 第一导电类型的给定区域经由电阻器连接到MOS晶体管的沟道，使得给定区域经由电阻器和MOS晶体管电连接到存储电容器的第一电极。

公开(公告)号：USRE36061E

公开(公告)日：1999-01-26

申请号：US542360

申请日：1995-10-12

申请人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans Dieter Oberle

发明人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans Dieter Oberle

IPC分类号： G11C11/4094 ,  G11C11/4096 ,  G11C29/18 ,  G11C29/30 ,  G11C29/00

CPC分类号： G11C29/30 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/18

摘要： An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.

摘要翻译： 集成半导体存储器包括具有以矩阵形式设置的存储单元的存储单元区，字线和内部位线，形成用于触发存储单元的内部位线对。 内部加权电路各自分配给内部位线对中的相应一个。 外部一对位线通常被分配给内部位线。 分离晶体管对分别被分配给内部位线对中的相应一个，用于将各个内部位线对与外部位线对电气分离。 位线解码器触发分离晶体管对。 提供外部加权电路。 鉴别器装置和预充电装置连接到外部位线对。 每对内部位线的内部位线彼此分开触发。 每对内部位线的内部位线彼此分开连接到外部位线对。

公开(公告)号：US5774014A

公开(公告)日：1998-06-30

申请号：US627568

申请日：1996-04-04

申请人： Johannes Stecker ,  Klaus Luther ,  Kurt Hoffmann ,  Oskar Kowarik

发明人： Johannes Stecker ,  Klaus Luther ,  Kurt Hoffmann ,  Oskar Kowarik

IPC分类号： G05F3/24 ,  G05F3/26 ,  H03K19/003 ,  H03K19/0185 ,  G05F1/10

CPC分类号： H03K19/00384 ,  G05F3/262

摘要： An integrated buffer circuit includes a first series circuit connected between a first supply potential and a second supply potential (ground). The first series circuit has a voltage-controlled first constant current source, a first field effect transistor having a gate forming an input of the buffer circuit, a circuit node between the first current source and the first field effect transistor forming an output of the buffer circuit, and a first control input for controlling the first current source with a reference potential having a constant potential difference relative to the first supply potential. A second series circuit is connected between the first supply potential and the second supply potential. The second series circuit has a first resistor, a second constant current source furnishing a current being independent of the first supply potential, and a circuit node between the first resistor and the second current source, establishing the reference potential and being connected to the first control input of the first current source.

摘要翻译： 集成缓冲电路包括连接在第一电源电位和第二电源电位（地）之间的第一串联电路。 第一串联电路具有电压控制的第一恒流源，第一场效应晶体管，其栅极形成缓冲电路的输入，第一电流源与第一场效应晶体管之间的电路节点，形成缓冲器的输出 电路和第一控制输入，用于以相对于第一电源电位具有恒定电位差的参考电位来控制第一电流源。 第二串联电路连接在第一电源电位和第二电源电位之间。 第二串联电路具有第一电阻器，提供独立于第一电源电位的电流的第二恒流源，以及第一电阻器和第二电流源之间的电路节点，建立参考电位并连接到第一控制器 输入第一个电流源。

公开(公告)号：US4885748A

公开(公告)日：1989-12-05

申请号：US168668

申请日：1988-03-16

申请人： Kurt Hoffmann ,  Hans-Dieter Oberle ,  Rainer Kraus ,  Oskar Kowarik ,  Manfred Paul

发明人： Kurt Hoffmann ,  Hans-Dieter Oberle ,  Rainer Kraus ,  Oskar Kowarik ,  Manfred Paul

IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C29/34

CPC分类号： G11C29/34

摘要： A method and circuit configuration for the parallel input of data items in the form of a test pattern into a block of a semiconductor memory having a plurality of storage cells. For test purposes, data items are simultaneously input in parallel into the storage cells.

摘要翻译： 一种用于将测试图形形式的数据项并行输入到具有多个存储单元的半导体存储器的块中的方法和电路配置。 为了测试目的，数据项同时并入输入到存储单元中。

公开(公告)号：US06627935B2

公开(公告)日：2003-09-30

申请号：US09767806

申请日：2001-01-22

申请人： Oskar Kowarik ,  Kurt Hoffman

发明人： Oskar Kowarik ,  Kurt Hoffman

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A resistive ferroelectric memory cell includes a selection transistor having first and second zones of a first conduction type. A storage capacitor has one electrode at a fixed cell-plate voltage and another electrode connected to the first zone of the selection transistor. A semiconductor substrate has a second conduction type opposite the first conduction type. The storage capacitor and the selection transistor are disposed in the semiconductor substrate. A resistor is disposed between the other electrode of the storage capacitor and the fixed cell-plate voltage. The resistor has a resistance R2 such that R3

摘要翻译： 电阻性强电介质存储单元包括具有第一和第二区的第一导电类型的选择晶体管。 存储电容器具有固定电池板电压的一个电极和连接到选择晶体管的第一区的另一电极。 半导体衬底具有与第一导电类型相反的第二导电类型。 存储电容器和选择晶体管设置在半导体衬底中。 在存储电容器的另一个电极和固定电池板电压之间设置电阻器。 该电阻具有电阻R2，使得R3 << R2 << R1，其中R1是选择晶体管的第一区与半导体衬底之间的pn结的反向电阻，而R3是第一区与第二区之间的电阻 选择晶体管的第二区域处于导通状态。

公开(公告)号：US06392918B2

公开(公告)日：2002-05-21

申请号：US09817578

申请日：2001-03-26

申请人： Georg Braun ,  Heinz Hönigschmid ,  Kurt Hoffmann ,  Oskar Kowarik ,  Thomas Röhr

发明人： Georg Braun ,  Heinz Hönigschmid ,  Kurt Hoffmann ,  Oskar Kowarik ,  Thomas Röhr

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.

摘要翻译： 用于产生用于读出的参考电压的电路和用于经由位线从铁电存储器的存储单元以恒定板电压读出的读取输出信号的评估。 在该电路中，参考电压装置由经受互补信号的作用的两个参考单元形成。 可以同时读出参考单元，以便在选择和评估装置中产生参考电压。

公开(公告)号：US5030861A

公开(公告)日：1991-07-09

申请号：US445687

申请日：1989-11-16

申请人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus

发明人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus

IPC分类号： H03K17/693 ,  G11C29/34 ,  G11C29/36 ,  G11C29/38 ,  H03K19/096 ,  H03K19/173

CPC分类号： G11C29/38 ,  G11C29/34 ,  G11C29/36 ,  H03K19/1736

摘要： A circuit gives each of the input signals at its inputs to a common circuit previously charged to a supply voltage through transfer transistors. When the logical condition is satisfied the common circuit remains charged; otherwise the charge changes. This is detected by a discriminator circuit and the result is indicated at the circuit output. The circuit may be of AND-, OR-, NAND- and NOR design.

摘要翻译： PCT No.PCT / DE88 / 00158 Sec。 371日期：一九八九年十一月十六日 102（e）日期1989年11月16日PCT提交1988年3月15日PCT Pub。 出版物WO88 / 07292 日期1988年9月22日。电路将其输入端的每个输入信号提供给预先通过传输晶体管充电到电源电压的公共电路。 当满足逻辑条件时，公共电路保持充电; 否则收费变动。 这由鉴频器电路检测，结果在电路输出端指示。 该电路可以是AND-，OR-，NAND-和NOR设计。

公开(公告)号：US06768667B2

公开(公告)日：2004-07-27

申请号：US10254693

申请日：2002-09-25

申请人： Kurt Hoffmann ,  Oskar Kowarik

发明人： Kurt Hoffmann ,  Oskar Kowarik

IPC分类号： G11C1124

CPC分类号： H01L27/1024 ,  G11C11/404

摘要： A DRAM memory cell having an isolation transistor formed from a bipolar transistor.

摘要翻译： 具有由双极晶体管形成的隔离晶体管的DRAM存储单元。

公开(公告)号：US06388917B2

公开(公告)日：2002-05-14

申请号：US09915983

申请日：2001-07-25

申请人： Kurt Hoffmann ,  Oskar Kowarik

发明人： Kurt Hoffmann ,  Oskar Kowarik

IPC分类号： G11C1115

CPC分类号： G11C11/16

摘要： A method for nondestructively reading memory cells of an MRAM memory, which includes steps of: determining a standard resistance of a memory cell at a voltage at which a resistance of the memory cell is independent of a stored content of the memory cell; determining an actual resistance of the memory cell at a voltage at which the resistance of the memory cell is dependent on the stored content of the memory cell; obtaining a normalized actual resistance of the memory cell by dividing the actual resistance by the standard resistance; obtaining a comparison result by comparing the normalized actual resistance with a reference value; and detecting the stored content of the memory cell dependent on the comparison result.

摘要翻译： 一种用于非破坏性地读取MRAM存储器的存储单元的方法，其包括以下步骤：以所述存储器单元的电阻独立于存储单元的存储内容的电压确定存储单元的标准电阻; 在存储单元的电阻取决于存储单元的存储内容的电压下确定存储单元的实际电阻; 通过将实际电阻除以标准电阻来获得存储单元的归一化实际电阻; 通过将标准化的实际电阻与参考值进行比较来获得比较结果; 以及根据比较结果检测存储单元的存储内容。

公开(公告)号：US5276643A

公开(公告)日：1994-01-04

申请号：US799907

申请日：1991-11-26

申请人： Kurt Hoffmann ,  Rainer Kraus ,  Oskar Kowarik

发明人： Kurt Hoffmann ,  Rainer Kraus ,  Oskar Kowarik

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C7/06

CPC分类号： G11C7/00 ,  G11C7/1006

摘要： An integrated semiconductor circuit includes word lines and bit lines. A memory region has at least one memory cell field with memory cells addressable through the word lines and the bit lines, and a number of evaluator circuits corresponding to the number of the bit lines. Each of the evaluator circuits is connected with one of the bit lines and divides the one bit line into two at least approximately identical bit line halves. Logic units of a block perform digital processing of data read-out of the memory region through the bit lines and evaluated. Each of the logic units is connected to the two bit line halves of one of the bit lines. Various operating modes of the block of logic units are selected with mode select signals.

摘要翻译： 集成半导体电路包括字线和位线。 存储器区域具有至少一个具有可通过字线和位线寻址的存储器单元的存储单元区域，以及与位线数量对应的多个求值器电路。 每个评估器电路与一个位线连接，并将一个位线分成两个至少近似相同的位线半部。 块的逻辑单元通过位线执行对存储器区域的数据读出的数字处理并进行评估。 每个逻辑单元连接到其中一个位线的两个位线半部。 通过模式选择信号选择逻辑单元块的各种操作模式。