公开(公告)号：US20090200651A1

公开(公告)日：2009-08-13

申请号：US11549641

申请日：2006-10-14

Applicant: Moriss Kung ,  Kwun-Yao Ho

Inventor： Moriss Kung ,  Kwun-Yao Ho

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/05599

Abstract: A multi-chip package structure is provided with a first chip, a substrate adjacent to the first chip, a plurality of contacts connecting the first chip and the substrate, a second chip disposed between the first chip and the substrate and connecting to the first chip, and a underfill film, wherein the underfill film covers the contact to isolate the contact from the second chip, wherein an empty space is defined by the second chip and the substrate so that the second chip does not contact the substrate.

Abstract translation: 多芯片封装结构设置有第一芯片，与第一芯片相邻的基板，连接第一芯片和基板的多个触点，设置在第一芯片和基板之间并连接到第一芯片的第二芯片 和底部填充膜，其中所述底部填充膜覆盖所述触点以将所述触点与所述第二芯片隔离，其中由所述第二芯片和所述基板限定空白空间，使得所述第二芯片不接触所述基板。

公开(公告)号：US07180166B2

公开(公告)日：2007-02-20

申请号：US10995380

申请日：2004-11-24

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L23/02 ,  H01L23/495 ,  H01L23/10 ,  H01L23/34

CPC classification number: H01L25/0657 ,  H01L25/105 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014

Abstract: A stacked multi-chip package comprising a substrate, a first chip, a lead frame, and a second chip is provided. The first chip is placed on and electrically connected with the substrate. The lead frame is placed on the substrate and forming a space therebeneath to accommodate the first chip. The second chip is placed to the lead frame and electrically connected with the substrate through the lead frame.

Abstract translation: 提供了包括基板，第一芯片，引线框架和第二芯片的堆叠多芯片封装。 第一芯片放置在基板上并与基板电连接。 引线框架放置在基板上并形成其下方的空间以容纳第一芯片。 第二芯片被放置在引线框架上并通过引线框架与基板电连接。

公开(公告)号：US07176559B2

公开(公告)日：2007-02-13

申请号：US10637045

申请日：2003-08-08

Applicant: Kwun Yao Ho ,  Moriss Kung ,  Terry Ku ,  Andy Liao

Inventor： Kwun Yao Ho ,  Moriss Kung ,  Terry Ku ,  Andy Liao

IPC: H01L23/02

CPC classification number: H01L23/367 ,  H01L21/563 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package includes a balanced-part structure. The condition of thermal stress of chips connected on a substrate decides the amount, locations, weights, and the material of at least a balanced-part fastened on a substrate. The balanced-part is fastened on the substrate to balance stress distribution before an adhering heat sinks process and a packaging molding compound process. The balanced-part also decreases thermal stress affection and avoid warpage defects of the integrated circuit packages.

Abstract translation: 集成电路封装包括平衡部分结构。 连接在基板上的芯片的热应力条件决定了至少固定在基板上的平衡部件的数量，位置，重量和材料。 平衡部分固定在基板上，以在粘附散热过程和包装模塑复合工艺之前平衡应力分布。 平衡部件还降低了热应力影响，并避免了集成电路封装的翘曲缺陷。

公开(公告)号：US20060071314A1

公开(公告)日：2006-04-06

申请号：US11205107

申请日：2005-08-17

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L23/02

CPC classification number: H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15322 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A cavity-down stacked multi-chip package with a plurality of packages stacked together is provided. The uppermost package has a circuit board with an opening, a heat spreader, and a chip. The heat spreader is positioned on the circuit board and covers the opening. The chip is positioned in the opening and adhered to a lower surface of the heat spreader. In addition, the chip is electrically connected to a lower surface of the circuit board through at least a conductive wire.

Abstract translation: 提供了具有堆叠在一起的多个封装的空腔向下堆叠多芯片封装。 最上面的封装具有带开口的电路板，散热器和芯片。 散热器位于电路板上并覆盖开口。 芯片位于开口处并粘附到散热器的下表面。 此外，芯片通过至少一根导线与电路板的下表面电连接。

公开(公告)号：US06972964B2

公开(公告)日：2005-12-06

申请号：US11042638

申请日：2005-01-25

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L23/538 ,  H05K1/18

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/056 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A module board has embedded chips and components. A substrate has at least one large cavity and at least one small cavity, in which the large cavity passes through the substrate and a passive component is set in the small cavity. A heat-dissipation sheet is set at the bottom of the substrate. A first adhesion layer bonds the bottom of the substrate to the heat-dissipation sheet. At least one IC chip is fixed in the large cavity of the substrate by a second adhesion layer. A dielectric filling layer covers the entire surface of the module board and fills all gaps, in which the dielectric filling layer has a plurality of micro vias to expose partial areas of the IC chip, the passive component and the substrate. At least one wiring pattern layer is formed on the dielectric filling layer and provide electrical connection among the IC chip, the passive component, and the substrate.

Abstract translation: 模块板具有嵌入式芯片和组件。 衬底具有至少一个大空腔和至少一个小空腔，其中大空腔通过衬底，并且将无源部件设置在小空腔中。 散热片设置在基板的底部。 第一粘附层将基底的底部粘合到散热片。 至少一个IC芯片通过第二粘合层固定在基板的大空腔中。 电介质填充层覆盖模块板的整个表面并且填充所有间隙，其中介电填充层具有多个微通孔以暴露IC芯片，无源部件和基板的部分区域。 在介电填充层上形成至少一个布线图案层，并且在IC芯片，无源元件和基板之间提供电连接。

公开(公告)号：US06951773B2

公开(公告)日：2005-10-04

申请号：US10249060

申请日：2003-03-13

Applicant: Kwun-Yo Ho ,  Moriss Kung

Inventor： Kwun-Yo Ho ,  Moriss Kung

IPC: H01L21/68 ,  H01L23/36 ,  H01L23/498 ,  H01L25/065 ,  H01L21/44

CPC classification number: H01L21/6835 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A structure of a chip package and a process thereof are provided. The process of the chip package makes use of the TFT-LCD panel or IC process to increase the circuit layout density for high electrical performance. First, a multi-layer interconnection structure with pads of high layout density and thin fine circuits is formed on a base substrate with a large-area and high co-planarity surface, wherein the base substrate is made of quartz or glass or ceramics. Then, a chip is located on the top surface of the multi-layer interconnection structure by flip-chip or wire-bonding technology. Then, a substrate or a heat sink is attached on the top surface of the multi-layer interconnection structure for being a stiffener and providing mechanical support. Finally, the base substrate is removed and contacts are attached on the bottom surface of the multi-layer interconnection structure.

Abstract translation: 提供了芯片封装的结构及其工艺。 芯片封装的过程利用TFT-LCD面板或IC工艺来增加电路布局密度以实现高电气性能。 首先，在具有大面积和高共面性表面的基底基板上形成具有高布局密度的焊盘和薄的精细电路的多层互连结构，其中基底由石英或玻璃或陶瓷制成。 然后，芯片通过倒装芯片或引线键合技术位于多层互连结构的顶表面上。 然后，将基板或散热器附接在多层互连结构的顶表面上，作为加强件并提供机械支撑。 最后，去除基底基板，并将触点附着在多层互连结构的底面上。

公开(公告)号：US20050189644A1

公开(公告)日：2005-09-01

申请号：US10980168

申请日：2004-11-04

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L23/053 ,  H01L23/13 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L23/13 ,  H01L23/49833 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/051 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A build-up layer packaging comprising a first ceramic substrate, a second ceramic substrate, and a circuit layer is provided. The first ceramic substrate has a through hole to dispose a die therein. The second ceramic substrate, attached to a common lower surface of the ceramic substrate and the die, further has a plurality of openings to expose the pads of the die. The openings are filled with plugs electrically connecting to the pads. The circuit layer is formed under the second ceramic substrate to transmit signals generated by the die outward.

Abstract translation: 提供了包括第一陶瓷基板，第二陶瓷基板和电路层的积层层封装。 第一陶瓷基板具有用于在其中配置模具的通孔。 附着在陶瓷基板和模具的公共下表面上的第二陶瓷基板还具有多个开口以暴露模具的焊盘。 开口填充有电连接到垫的插头。 电路层形成在第二陶瓷衬底下方，以将由芯片产生的信号向外传输。

公开(公告)号：US06916687B2

公开(公告)日：2005-07-12

申请号：US10605305

申请日：2003-09-22

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L21/60 ,  H01L23/485 ,  H01L21/50 ,  H01L21/48

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2224/05671 ,  H01L2924/00014

Abstract: A bump process for fabricating bumps and an underfill layer on the active surface of a chip inside a flip chip package is disclosed. An adhesive layer is formed on each of the die pads of the chip. Thereafter, a plurality of bump balls are scattered on the active surface of the chip. The bump balls are vibrated such that only one bump ball is attached to the adhesive layer of each die pad. After removing the un-attached bump balls from the active surface of the chip, an underfill material is applied on the active surface of the chip to encapsulate the bump balls but expose their top surfaces. Thus, the bump process is capable of increasing the reliability of the flip chip package and lower the overall fabrication cost of the flip chip package.

Abstract translation: 公开了一种用于在倒装芯片封装内的芯片的有源表面上制造凸块和底部填充层的凸块工艺。 在芯片的每个芯片焊盘上形成粘合剂层。 此后，多个凸块球散布在芯片的有源表面上。 碰撞球被振动，使得只有一个凸块球附接到每个芯片焊盘的粘合剂层。 在从芯片的有源表面去除未附着的凸块球之后，将底部填充材料施加在芯片的有源表面上以封装凸块球，但暴露其顶表面。 因此，凸块工艺能够提高倒装芯片封装的可靠性并降低倒装芯片封装的整体制造成本。

公开(公告)号：US20050035453A1

公开(公告)日：2005-02-17

申请号：US10739638

申请日：2003-12-17

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/48 ,  H05K3/34

CPC classification number: H05K3/3478 ,  H01L21/4853 ,  H01L24/11 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H05K2203/0338 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A bump transfer fixture for accommodating a plurality of bumps is provided. The bump transfer fixture includes a transfer plate having a plurality of fix structures. The plurality of fix structures are disposed on the surface of the transfer plate. Each of the plurality of fix structures accommodates one of the bumps. The fix structures can be concave or convex structures. By using the transfer plate to form the bumps, no photolithography technology is used to form the patterned photoresist layer. Hence, the bump transfer process is much simpler and faster. Therefore, the present invention effectively reduces the cost and time for the bump transfer process.

Abstract translation: 提供了用于容纳多个凸块的凸块转移夹具。 凸块转移夹具包括具有多个固定结构的转印板。 多个固定结构设置在转印板的表面上。 多个固定结构中的每一个容纳其中一个凸块。 固定结构可以是凹形或凸形结构。 通过使用转印板来形成凸块，不使用光刻技术来形成图案化的光致抗蚀剂层。 因此，凸块转移过程要简单得多，速度更快。 因此，本发明有效地降低了凸块传递过程的成本和时间。

公开(公告)号：US06743659B2

公开(公告)日：2004-06-01

申请号：US10150084

申请日：2002-05-20

Applicant: Moriss Kung ,  Kwun-Yao Ho

Inventor： Moriss Kung ,  Kwun-Yao Ho

IPC: H01L2144

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/096 ,  H05K2203/0191

Abstract: A method for manufacturing multi-layer package substrates is shown. A substrate with a first side and a second side is first provided, and a layer of release film is formed on the first side and second side of the substrate. After drilling a plurality of through holes on the substrate bonded to the release film and plugging the through holes with a conductive material, the release film is removed. A first copper film is formed on the first and second side of the substrate. First, circuit layer patterns are formed on the first and second side of the substrate through photolithography and etching processes. After coating an build-up layer on the first and second side of the substrate and drilling the build-up layers with a laser to form counter vias on the first side and second side of the substrate, a copper seed layer is formed on the inner surfaces of the counter vias. Second circuit layer patterns are formed on the first side and second side of the substrate. Finally, contact pads are formed on the first side and second side of the substrate.

Abstract translation: 示出了制造多层封装衬底的方法。 首先设置具有第一侧和第二侧的基板，并且在基板的第一侧面和第二侧上形成剥离膜层。 在与剥离膜接合的基板上钻出多个通孔并用导电材料堵塞通孔之后，去除脱模膜。 在基板的第一和第二侧上形成第一铜膜。 首先，通过光刻和蚀刻工艺在衬底的第一和第二侧上形成电路层图案。 在基板的第一和第二侧上涂覆积层之后，用激光钻积层，在基板的第一面和第二面上形成反向通孔，在内层形成铜籽晶层 计数器通孔的表面。 在衬底的第一侧面和第二侧上形成第二电路层图案。 最后，在衬底的第一侧和第二侧上形成接触焊盘。