公开(公告)号：US08692223B2

公开(公告)日：2014-04-08

申请号：US13596807

申请日：2012-08-28

申请人： Ji-Won Moon ,  Moon-Sig Joo ,  Sung-Hoon Lee ,  Jung-Nam Kim

发明人： Ji-Won Moon ,  Moon-Sig Joo ,  Sung-Hoon Lee ,  Jung-Nam Kim

IPC分类号： H01L47/00

CPC分类号： H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1641

摘要： A resistance variable memory device includes: a first electrode; a second electrode; a resistance variable layer interposed between the first electrode and the second electrode; and nano particles that are disposed in the resistance variable layer and have a lower dielectric constant than the resistance variable layer.

摘要翻译： 电阻可变存储器件包括：第一电极; 第二电极; 介于所述第一电极和所述第二电极之间的电阻变化层; 和纳米颗粒，其设置在电阻变化层中并具有比电阻变化层低的介电常数。

公开(公告)号：US08399323B2

公开(公告)日：2013-03-19

申请号：US13244247

申请日：2011-09-23

申请人： Ki-Hong Lee ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

发明人： Ki-Hong Lee ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/2236 ,  H01L27/11578 ,  H01L27/11582

摘要： A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.

摘要翻译： 一种用于制造垂直通道型非易失性存储器件的方法，包括：在衬底上交替堆叠多个层间绝缘层和多个栅电极导电层; 蚀刻层间绝缘层和栅电极导电层以形成暴露衬底的沟槽; 在包括沟道沟槽的所得结构上形成未掺杂的第一沟道层; 通过等离子体掺杂工艺对具有杂质的第一沟道层进行掺杂; 以及用第二通道层填充沟槽。

公开(公告)号：US20120021574A1

公开(公告)日：2012-01-26

申请号：US13244247

申请日：2011-09-23

申请人： Ki-Hong LEE ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

发明人： Ki-Hong LEE ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/2236 ,  H01L27/11578 ,  H01L27/11582

摘要： A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.

摘要翻译： 一种用于制造垂直通道型非易失性存储器件的方法，包括：在衬底上交替堆叠多个层间绝缘层和多个栅电极导电层; 蚀刻层间绝缘层和栅电极导电层以形成暴露衬底的沟槽; 在包括沟道沟槽的所得结构上形成未掺杂的第一沟道层; 通过等离子体掺杂工艺对具有杂质的第一沟道层进行掺杂; 以及用第二通道层填充沟槽。

公开(公告)号：US08039337B2

公开(公告)日：2011-10-18

申请号：US13047258

申请日：2011-03-14

申请人： Heung-Jae Cho ,  Moon-Sig Joo ,  Yong-Soo Kim ,  Won-Joon Choi

发明人： Heung-Jae Cho ,  Moon-Sig Joo ,  Yong-Soo Kim ,  Won-Joon Choi

IPC分类号： H01L21/8238

CPC分类号： H01L21/28282 ,  H01L21/28273

摘要： A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.

公开(公告)号：US20110165769A1

公开(公告)日：2011-07-07

申请号：US13047258

申请日：2011-03-14

申请人： Heung-Jae CHO ,  Moon-Sig Joo ,  Yong-Soo Kim ,  Won-Joon Choi

发明人： Heung-Jae CHO ,  Moon-Sig Joo ,  Yong-Soo Kim ,  Won-Joon Choi

IPC分类号： H01L21/28

CPC分类号： H01L21/28282 ,  H01L21/28273

摘要： A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.

摘要翻译： 具有控制电荷存储层中的电荷转移的阻挡层的非易失性存储器件包括具有与电荷存储层接触的第一阻挡层和第一阻挡层上的第二阻挡层的阻挡层，其中第一阻塞 层具有比第二阻挡层更大的能带隙，并且第二阻挡层具有比第一阻挡层更大的介电常数。

公开(公告)号：US07928493B2

公开(公告)日：2011-04-19

申请号：US12430481

申请日：2009-04-27

申请人： Heung-Jae Cho ,  Moon-Sig Joo ,  Yong-Soo Kim ,  Won-Joon Choi

发明人： Heung-Jae Cho ,  Moon-Sig Joo ,  Yong-Soo Kim ,  Won-Joon Choi

IPC分类号： H01L29/788

CPC分类号： H01L21/28282 ,  H01L21/28273

摘要： A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.

摘要翻译： 具有控制电荷存储层中的电荷转移的阻挡层的非易失性存储器件包括具有与电荷存储层接触的第一阻挡层和第一阻挡层上的第二阻挡层的阻挡层，其中第一阻塞 层具有比第二阻挡层更大的能带隙，并且第二阻挡层具有比第一阻挡层更大的介电常数。

公开(公告)号：US20100317166A1

公开(公告)日：2010-12-16

申请号：US12493439

申请日：2009-06-29

申请人： Ki-Hong Lee ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

发明人： Ki-Hong Lee ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/2236 ,  H01L27/11578 ,  H01L27/11582

摘要： A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.

摘要翻译： 一种用于制造垂直通道型非易失性存储器件的方法，包括：在衬底上交替堆叠多个层间绝缘层和多个栅电极导电层; 蚀刻层间绝缘层和栅电极导电层以形成暴露衬底的沟槽; 在包括沟道沟槽的所得结构上形成未掺杂的第一沟道层; 通过等离子体掺杂工艺对具有杂质的第一沟道层进行掺杂; 以及用第二通道层填充沟槽。

公开(公告)号：US20100283096A1

公开(公告)日：2010-11-11

申请号：US12640491

申请日：2009-12-17

申请人： Sung-Jin Whang ,  Moon-Sig Joo ,  Kwon Hong ,  Jung-Yeon Lim ,  Won-Kyu Kim ,  Bo-Min Seo ,  Kyoung-Eun Chang

发明人： Sung-Jin Whang ,  Moon-Sig Joo ,  Kwon Hong ,  Jung-Yeon Lim ,  Won-Kyu Kim ,  Bo-Min Seo ,  Kyoung-Eun Chang

IPC分类号： H01L29/792 ,  H01L23/48 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/321 ,  H01L21/7685 ,  H01L24/02 ,  H01L27/10873 ,  H01L29/413 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881 ,  H01L2224/0401 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/12032 ,  H01L2924/00

摘要： A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.

摘要翻译： 一种半导体器件，包括导电层，形成在导电层上的扩散阻挡层，包括难熔金属化合物，并在表面处理之后获得，以及形成在扩散阻挡层上的金属硅化物层。 通过表面处理增加扩散阻挡层的表面能，可以改善扩散阻挡层和金属硅化物层之间的粘合性。 因此，尽管金属硅化物层在高温工艺中熔合，但是可以防止在扩散阻挡层和金属硅化物层之间的界面处产生空隙。 此外，通过表面处理增加导电层的表面能，可以增加导电层与扩散阻挡层之间的粘合性。

公开(公告)号：US20090227116A1

公开(公告)日：2009-09-10

申请号：US12347289

申请日：2008-12-31

申请人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi ,  Sung Jin Whang

发明人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi ,  Sung Jin Whang

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/513 ,  H01L29/792

摘要： A method for manufacturing a non-volatile memory device having a charge trap layer comprises in one embodiment: forming a first dielectric layer over a semiconductor substrate; forming a second dielectric layer having a higher dielectric constant than that of the first dielectric layer over the first dielectric layer; forming a nitride buffer layer for preventing an interfacial reaction over the second dielectric layer; forming a third dielectric layer by supplying a radical oxidation source onto the nitride buffer layer to oxidize the nitride buffer layer, thereby forming a tunneling layer comprising the first, second, and third dielectric layers; and forming a charge trap layer, a shielding layer, and a control gate electrode layer over the tunneling layer.

摘要翻译： 制造具有电荷陷阱层的非易失性存储器件的方法包括在一个实施例中：在半导体衬底上形成第一介电层; 在所述第一介电层上形成具有比所述第一介电层的介电常数更高的介电常数的第二电介质层; 形成用于防止所述第二介电层上的界面反应的氮化物缓冲层; 通过向所述氮化物缓冲层上提供自由基氧化源以氧化所述氮化物缓冲层而形成第三电介质层，从而形成包括所述第一，第二和第三电介质层的隧道层; 并在隧道层上形成电荷陷阱层，屏蔽层和控制栅极电极层。

公开(公告)号：US20090108334A1

公开(公告)日：2009-04-30

申请号：US12164720

申请日：2008-06-30

申请人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Yong Top Kim ,  Jae Young Park ,  Ki Hong Lee

发明人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Yong Top Kim ,  Jae Young Park ,  Ki Hong Lee

IPC分类号： H01L21/28 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11565 ,  H01L27/11568

摘要： A charge trapping device includes a plurality of isolation layers, a plurality of charge trapping layers, a blocking layer, and a control gate electrode. The isolation layers define active regions, and the isolation layers and active regions extend as respective stripes along a first direction on a semiconductor substrate. The charge trapping layers are disposed on the active regions in island forms where the charge trapping layers are separated from each other in the first direction and disposed on the respective active regions between the isolation layers in a second direction perpendicular to the first direction. The blocking layer is disposed on the isolation layers and the charge trapping layers. The control gate electrode is disposed on the charge trapping layer.

摘要翻译： 电荷俘获装置包括多个隔离层，多个电荷俘获层，阻挡层和控制栅电极。 隔离层限定有源区，并且隔离层和有源区沿着半导体衬底上的第一方向作为相应条延伸。 电荷捕获层以岛形式设置在有源区，其中电荷捕获层在第一方向上彼此分离，并且在垂直于第一方向的第二方向上设置在隔离层之间的相应有源区上。 阻挡层设置在隔离层和电荷俘获层上。 控制栅电极设置在电荷捕获层上。