公开(公告)号：US06275929B1

公开(公告)日：2001-08-14

申请号：US09318631

申请日：1999-05-26

Applicant: Rivka Blum ,  Meny Yanni

Inventor： Rivka Blum ,  Meny Yanni

IPC: G06F938

CPC classification number: G06F9/30145 ,  G06F9/30079 ,  G06F9/3836

Abstract: A method for insertion of a dynamic number of implicit nop instructions by the microprocessor at run-time. The implicit nop instructor is a no operation instruction which is executed by the microprocessor without placing an actual nop instruction in the program itself. The method of the present invention enables the appropriate number of implicit nop instructions to be automatically calculated and executed for every occurrence of a multi-cycle instruction. Hereinafter, the term automatically refers to a process which occurs without the direct intervention of the programmer or higher-language compiler. The appropriate number of implicit nop instructions is automatically calculated by the microprocessor, by subtracting the number of IDSI from the total number of delay-slots which are required. The number of IDSI is preferably determined by the assembler, and then made available to the microprocessor. More preferably, this number is placed in a delay-slot field in the coded instruction by the assembler, and is then retrieved from the delay-slot field by the microprocessor. Thus, the method of the present invention enables the microprocessor to automatically insert the required number of implicit nop instructions, without requiring extra memory resources and without forcing the programmer or higher-language compiler to insert nop instructions into each unused delay-slot.

Abstract translation: 用于在运行时由微处理器插入动态数量的隐含nop指令的方法。 隐式nop指导者是由微处理器执行的无操作指令，而不将实际的nop指令放在程序本身中。 本发明的方法使得可以针对多周期指令的每次出现自动地计算和执行适当数量的隐含nop指令。 在下文中，该术语自动指的是在没有程序员或高级语言编译器的直接干预的情况下发生的过程。 由微处理器自动计算适当数量的隐含nop指令，通过从需要的延迟时隙的总数中减去IDSI的数量。 IDSI的数量优选由汇编器确定，然后使其可用于微处理器。 更优选地，该编号由汇编器置于编码指令的延迟时隙字段中，然后由微处理器从延迟时隙字段中检索。 因此，本发明的方法使得微处理器能够自动地插入所需数量的隐含的nop指令，而不需要额外的存储器资源，并且不强制程序员或高级语言编译器将nop指令插入每个未使用的延迟时隙。

公开(公告)号：US20120327703A1

公开(公告)日：2012-12-27

申请号：US13489699

申请日：2012-06-06

Applicant: Meny Yanni

Inventor： Meny Yanni

IPC: G11C11/413 ,  G11C7/08 ,  G06F12/08 ,  G11C7/10

CPC classification number: G11C11/419 ,  G06F13/16 ,  G06F13/1668 ,  G11C7/00 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005

Abstract: Systems and methods are provided for a random access memory controller. A random access memory controller includes a column multiplexer and sense amplifier pair, where the column multiplexer and sense amplifier pair includes a column multiplexer and a sense amplifier that are configured to utilize common circuitry. The common circuitry is shared between the column multiplexer and the sense amplifier so that the memory controller includes a single instance of the common circuitry for the column multiplexer and sense amplifier pair. The common circuitry includes a common pre-charge circuit, a common equalizer, or a common keeper circuit.

Abstract translation: 为随机存取存储器控制器提供系统和方法。 随机存取存储器控制器包括列复用器和读出放大器对，其中列多路复用器和读出放大器对包括配置为利用公共电路的列多路复用器和读出放大器。 公共电路在列多路复用器和读出放大器之间共享，使得存储器控制器包括用于列复用器和读出放大器对的公共电路的单一实例。 公共电路包括公共预充电电路，公共均衡器或公共保持器电路。

公开(公告)号：US08913420B2

公开(公告)日：2014-12-16

申请号：US13489699

申请日：2012-06-06

Applicant: Meny Yanni

Inventor： Meny Yanni

IPC: G11C11/00 ,  G11C11/4091 ,  G11C11/419 ,  G11C7/12 ,  G11C11/4094 ,  G11C7/06 ,  G11C7/00 ,  G06F13/16

CPC classification number: G11C11/419 ,  G06F13/16 ,  G06F13/1668 ,  G11C7/00 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005

Abstract: Systems and methods are provided for a random access memory controller. A random access memory controller includes a column multiplexer and sense amplifier pair, where the column multiplexer and sense amplifier pair includes a column multiplexer and a sense amplifier that are configured to utilize common circuitry. The common circuitry is shared between the column multiplexer and the sense amplifier so that the memory controller includes a single instance of the common circuitry for the column multiplexer and sense amplifier pair. The common circuitry includes a common pre-charge circuit, a common equalizer, or a common keeper circuit.

Abstract translation: 为随机存取存储器控制器提供系统和方法。 随机存取存储器控制器包括列复用器和读出放大器对，其中列多路复用器和读出放大器对包括配置为利用公共电路的列多路复用器和读出放大器。 公共电路在列多路复用器和读出放大器之间共享，使得存储器控制器包括用于列复用器和读出放大器对的公共电路的单一实例。 公共电路包括公共预充电电路，公共均衡器或公共保持器电路。

公开(公告)号：US06453407B1

公开(公告)日：2002-09-17

申请号：US09247686

申请日：1999-02-10

Applicant: Yoav Lavi ,  Amnon Rom ,  Robert Knuth ,  Rivka Blum ,  Meny Yanni ,  Haim Granot ,  Anat Hershko ,  Georgiy Shenderovitch ,  Elliot Cohen ,  Eran Weingatren

Inventor： Yoav Lavi ,  Amnon Rom ,  Robert Knuth ,  Rivka Blum ,  Meny Yanni ,  Haim Granot ,  Anat Hershko ,  Georgiy Shenderovitch ,  Elliot Cohen ,  Eran Weingatren

IPC: G06F922

CPC classification number: G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3885

Abstract: A method for executing instructions in a data processor and improvements to data processor design, which combine the advantages of regular processor architecture and Very Long Instruction Word architecture to increase execution speed and ease of programming, while reducing power consumption. Instructions each consisting of a number of operations to be performed in parallel are defined by the programmer, and their corresponding execution unit controls are generated at compile time and loaded prior to program execution into a dedicated array in processor memory. Subsequently, the programmer invokes reference instructions to call these defined instructions, and passes parameters from regular instructions in program memory. As the regular instructions propogate down the processor's pipeline, they are replaced by the appropriate controls fetched from the dedicated array in processor memory, which then go directly to the execution unit for execution. These instructions may be redefined while the program is running. In this way the processor benefits from the speed of parallel processing without the chip area and power consumption overhead of a wide program memory bus and multiple instruction decoders. A simple syntax for defining instructions, similar to that of the C programming language is presented.

Abstract translation: 一种用于在数据处理器中执行指令并改进数据处理器设计的方法，其结合了常规处理器架构和超长指令字架构的优点，以提高执行速度和易于编程，同时降低功耗。 由并行执行的多个操作组成的指令由程序员定义，并且它们相应的执行单元控制在编译时生成并在程序执行之前加载到处理器存储器中的专用阵列中。 随后，程序员调用参考指令来调用这些定义的指令，并从程序存储器中的常规指令传递参数。 由于常规指令会降低处理器的流水线，所以它们将被从处理器存储器中专用阵列中提取的相应控件所取代，然后直接执行单元执行。 这些指令可能在程序运行时被重新定义。 以这种方式，处理器受益于并行处理的速度，而没有宽的程序存储器总线和多个指令解码器的芯片面积和功耗开销。 介绍了一种用于定义与C编程语言相似的指令的简单语法。