公开(公告)号：US07609305B2

公开(公告)日：2009-10-27

申请号：US11101195

申请日：2005-04-06

Applicant: Eugene Fainstain ,  Shlomo Polonsky ,  Miriam Fraenkel ,  Yoav Lavi

Inventor： Eugene Fainstain ,  Shlomo Polonsky ,  Miriam Fraenkel ,  Yoav Lavi

IPC: H04N9/64 ,  H04N5/225

CPC classification number: H04N9/045 ,  H04N5/3572

Abstract: Embodiments of the current invention provide for systems and methods for correcting shading effects in image sensors. More specifically, but not by way of limitation, embodiments of the current invention provide methods and systems for dynamically correcting shading effects for digitally converted outputs from individual pixels on a pixel array in the image sensor, wherein the shading correction may be calculated according to a function of an elliptical-type equation from the radial location of the pixel on the pixel array. In embodiments of the present invention, the correction is performed at the Bayer domain before demosaicing processing to provide for accuracy of shading correction and low power consumption.

Abstract translation: 本发明的实施例提供了用于校正图像传感器中的阴影效应的系统和方法。 更具体地但不是限制，本发明的实施例提供了用于动态校正图像传感器中的像素阵列上的各个像素的数字转换输出的阴影效果的方法和系统，其中阴影校正可以根据 来自像素阵列上的像素的径向位置的椭圆型方程的函数。 在本发明的实施例中，在去马赛克处理之前在拜耳域执行校正以提供阴影校正和低功耗的精度。

公开(公告)号：US08154636B2

公开(公告)日：2012-04-10

申请号：US12096943

申请日：2006-12-17

Applicant: Elchanan Rappaport ,  Yoav Lavi ,  David Drori ,  Uri Kinrot

Inventor： Elchanan Rappaport ,  Yoav Lavi ,  David Drori ,  Uri Kinrot

IPC: H04N3/14 ,  H04N5/335

CPC classification number: G06T5/003 ,  G06T5/20 ,  G06T5/50 ,  G06T2200/28 ,  G06T2207/10024

Abstract: An image enhancement circuit (26, 60, 190, 260) includes an input interface (64, 262), which is operative to accept a stream of input pixel values belonging to pixels (32) of an input image. The input image includes a plurality of different input sub-images including respective subsets of the pixels, such that the input pixel values of the pixels in the different input sub-images are interleaved in the stream. A plurality of filter cells (92, 144, 206, 222, 238, 364) are connected in a two-dimensional array configuration and are arranged to separately filter the input pixel values of each of the input sub-images with respective two-dimensional deconvolution kernels so as produce respective output sub-images that include output pixel values. A multiplexer (88, 332) is coupled to multiplex together the output pixel values of the output sub-images so as to produce a filtered output image.

Abstract translation: 图像增强电路（26,60,190,260）包括输入接口（64,262），其可操作以接受属于输入图像的像素（32）的输入像素值的流。 输入图像包括包括像素的各个子集的多个不同的输入子图像，使得不同输入子图像中的像素的输入像素值在流中交错。 多个滤波器单元（92,144,206,222,238,364）以二维阵列配置连接，并且被布置为分别对各个输入子图像的输入像素值进行相应的二维 反卷积核，从而产生包括输出像素值的各个输出子图像。 多路复用器（88,332）被耦合以将输出子图像的输出像素值复用在一起以产生滤波后的输出图像。

公开(公告)号：US07689047B2

公开(公告)日：2010-03-30

申请号：US11407688

申请日：2006-04-19

Applicant: Mickey Bahar ,  Yoav Lavi

Inventor： Mickey Bahar ,  Yoav Lavi

IPC: G06K9/36

CPC classification number: H04N19/423 ,  H04N19/60

Abstract: A method of compressing an image according to an image compression algorithm includes sequentially receiving pixel values into a buffers bank in line-by-line order. The image includes a plurality of pixels arranged into lines and columns. Each pixel has a pixel value associated therewith. Each line has L pixels. The image compression algorithm operates on blocks of pixels, each block having N lines and M columns. The method also includes storing each block-line of pixel values in a buffer of the buffers bank. A block-line includes M consecutive pixels of a line. The method also includes, for each block-line, storing a pointer to the buffer in which the block-line is stored and reading block-lines out of the buffers bank to a compression engine, wherein the block-lines are read out of the buffers bank in an order that is different from the line-by-line order in which the block-lines were received into the buffers bank. The method further includes compressing the image according to the image compression algorithm and displaying the image.

Abstract translation: 根据图像压缩算法压缩图像的方法包括以逐行顺序顺序地将像素值接收到缓冲器组中。 图像包括排列成行和列的多个像素。 每个像素具有与其相关联的像素值。 每行都有L个像素。 图像压缩算法对像素块进行操作，每个块具有N行和M列。 该方法还包括将每个像素值的块行存储在缓冲器组的缓冲器中。 块线包括一行的M个连续像素。 该方法还包括对于每个块行，存储指向缓冲器的指针，其中存储块行，并且将缓冲器组中的块行读出到压缩引擎，其中，块线从 缓冲器以与将块线路接收到缓冲器组中的逐行顺序不同的顺序存储。 该方法还包括根据图像压缩算法压缩图像并显示图像。

公开(公告)号：US20090254697A1

公开(公告)日：2009-10-08

申请号：US12119197

申请日：2008-05-12

Applicant: Avidan Akerib ,  Eli Ehrman ,  Yoav Lavi ,  Moshe Meyassed

Inventor： Avidan Akerib ,  Eli Ehrman ,  Yoav Lavi ,  Moshe Meyassed

IPC: G06F12/00

CPC classification number: G11C7/1006

Abstract: An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.

Abstract translation: 集成电路器件包括半导体衬底和随机存取存储器（RAM）单元阵列，其被布置在第一列中的衬底上，并被配置为存储数据。 设备中的计算部分包括相关存储器单元，其被布置在第二列中的衬底上，其与RAM单元的相应的第一列对齐并且与相应的第一列通信，以便从阵列接收数据 并且对数据执行关联计算。

公开(公告)号：US20080158396A1

公开(公告)日：2008-07-03

申请号：US11835275

申请日：2007-08-07

Applicant: Eugene Fainstain ,  Artyon Tonkikh ,  Yoav Lavi

Inventor： Eugene Fainstain ,  Artyon Tonkikh ,  Yoav Lavi

IPC: H04N9/64

CPC classification number: H04N5/3675 ,  H04N5/361 ,  H04N5/367 ,  H04N9/045 ,  H04N2209/046

Abstract: A method for enhancing an image read from an image sensor in the digital domain includes analyzing a row or a column of the image; determining the row or column is defective; and replacing the row or the column with information from adjacent portions of the image when the row or image is found defective.

Abstract translation: 用于增强从数字域中的图像传感器读取的图像的方法包括分析图像的行或列; 确定行或列是有缺陷的; 并且当行或图像被发现有缺陷时，使用来自图像的相邻部分的信息来替换行或列。

公开(公告)号：US6108240A

公开(公告)日：2000-08-22

申请号：US243977

申请日：1999-02-04

Applicant: Yoav Lavi ,  Oleg Dadashev

Inventor： Yoav Lavi ,  Oleg Dadashev

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A method and apparatus for erasing a single floating gate transistor in an array of floating gate transistors is provided. A selected floating gate transistor, which is located in a first row and a first column of the array, is erased as follows. A low voltage V.sub.LOW (e.g., 0 Volts) is applied to the gate of each transistor in the first row of the array. An erase voltage V.sub.ERASE (e.g., 8 Volts) is applied to the drain of each transistor in the first column of the array. An intermediate voltage V.sub.INT (e.g., 3 Volts) is applied to the source of each transistor in the array, as well as to the drain of each transistor of the array that is not in the first column. Under these conditions, only the selected floating gate transistor is erased. Other floating gate transistors in the first column are not erased because the gate-to-drain voltages of these transistors are limited by the intermediate voltage V.sub.INT applied to their gates.

Abstract translation: 提供了一种用于擦除浮置栅极晶体管阵列中的单个浮栅晶体管的方法和装置。 位于阵列的第一列和第一列中的选择的浮置栅极晶体管被擦除如下。 将低电压VLOW（例如，0伏）施加到阵列的第一行中的每个晶体管的栅极。 将擦除电压VERASE（例如，8伏）施加到阵列的第一列中的每个晶体管的漏极。 将中间电压VINT（例如3伏特）施加到阵列中的每个晶体管的源极以及阵列中不在第一列中的每个晶体管的漏极。 在这些条件下，只有所选择的浮栅晶体管被擦除。 由于这些晶体管的栅极至漏极电压受到施加到其栅极的中间电压VINT的限制，第一列中的其他浮置栅极晶体管不会被擦除。

公开(公告)号：US20100172190A1

公开(公告)日：2010-07-08

申请号：US12211919

申请日：2008-09-17

Applicant: Yoav Lavi ,  Eli Ehrman ,  Avidan Akerib

Inventor： Yoav Lavi ,  Eli Ehrman ,  Avidan Akerib

IPC: G11C7/00 ,  G11C7/06

CPC classification number: G11C7/1006 ,  G11C7/02 ,  G11C11/412 ,  G11C15/04 ,  G11C15/043

Abstract: Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memory circuits are standard or slightly modified SRAM and DRAM cells, or computing memory arrays (CAMs).

Abstract translation: 使用标准存储器电路来执行存储在存储器中的数据与引入到存储器中的数据之间的积和积函数。 产品总和功能以与标准存储器读取操作基本类似的方式执行。 存储器电路是标准或略微修改的SRAM和DRAM单元，或计算存储器阵列（CAM）。

公开(公告)号：US20100039524A1

公开(公告)日：2010-02-18

申请号：US12504560

申请日：2009-07-16

Applicant: Uri Kinrot ,  Yoav Lavi ,  Elchanan Rappaport

Inventor： Uri Kinrot ,  Yoav Lavi ,  Elchanan Rappaport

IPC: H04N5/228

CPC classification number: H04N21/435 ,  H04N5/23229 ,  H04N5/335 ,  H04N21/235 ,  H04N21/2353

Abstract: A method and apparatus for processing an image includes a buffer memory, which is configured to receive and store an input data stream including multiple image lines and one or more embedded data lines, which are interleaved with the image lines and include metadata that are not a part of the image. An image processor receives the input pixel values in succession from the buffer memory and processes the input pixel values so as to generate an output data stream including output pixel values, which are different from the input pixel values. A processing controller detects the one or more embedded data lines and controls the image processor, responsively to detecting the one or more embedded data lines, so that the embedded data lines pass through the image processor without modification of the metadata and are interleaved with the image lines of the output pixel values in the output data stream.

Abstract translation: 用于处理图像的方法和装置包括缓冲存储器，其被配置为接收和存储与图像行交错的包括多个图像行和一个或多个嵌入数据线的输入数据流，并且包括不是 图像的一部分。 图像处理器从缓冲存储器连续地接收输入像素值，并处理输入像素值，以便生成包括与输入像素值不同的输出像素值的输出数据流。 处理控制器响应于检测一个或多个嵌入数据线而检测一个或多个嵌入数据线并控制图像处理器，使得嵌入的数据线在不修改元数据的情况下通过图像处理器并与图像交错 输出数据流中的输出像素值的行。

公开(公告)号：US20090254694A1

公开(公告)日：2009-10-08

申请号：US12113475

申请日：2008-05-01

Applicant: Eli Ehrman ,  Yoav Lavi ,  Avidan Akerib

Inventor： Eli Ehrman ,  Yoav Lavi ,  Avidan Akerib

IPC: G06F12/00

CPC classification number: G11C7/1006

Abstract: A method for data processing includes accepting input data words including bits for storage in a memory, which includes multiple memory cells arranged in rows and columns. The accepted data words are stored so that the bits of each data word are stored in more than a single row of the memory. A data processing operation is performed on the stored data words by applying a sequence of one or more bit-wise operations to at least one row of the memory, so as to produce a result that is stored in one or more of the rows of the memory.

Abstract translation: 一种用于数据处理的方法包括接收包括用于存储在存储器中的位的输入数据字，其包括以行和列排列的多个存储器单元。 存储所接受的数据字，使得每个数据字的位被存储在存储器的多行中。 对存储的数据字执行数据处理操作，通过对存储器的至少一行施加一个或多个逐位操作的序列，以产生存储在存储器的一行或多行中的结果 记忆。

公开(公告)号：US20090128666A1

公开(公告)日：2009-05-21

申请号：US12096943

申请日：2006-12-17

Applicant: Elchanan Rappaport ,  Yoav Lavi ,  David Drori ,  Uri Kinrot

Inventor： Elchanan Rappaport ,  Yoav Lavi ,  David Drori ,  Uri Kinrot

IPC: H04N5/217

CPC classification number: G06T5/003 ,  G06T5/20 ,  G06T5/50 ,  G06T2200/28 ,  G06T2207/10024

Abstract: An image enhancement circuit (26, 60, 190, 260) includes an input interface (64, 262), which is operative to accept a stream of input pixel values belonging to pixels (32) of an input image. The input image includes a plurality of different input sub-images including respective subsets of the pixels, such that the input pixel values of the pixels in the different input sub-images are interleaved in the stream. A plurality of filter cells (92, 144, 206, 222, 238, 364) are connected in a two-dimensional array configuration and are arranged to separately filter the input pixel values of each of the input sub-images with respective two-dimensional deconvolution kernels so as produce respective output sub-images that include output pixel values. A multiplexer (88, 332) is coupled to multiplex together the output pixel values of the output sub-images so as to produce a filtered output image.

Abstract translation: 图像增强电路（26,60,190,260）包括输入接口（64,262），其可操作以接受属于输入图像的像素（32）的输入像素值的流。 输入图像包括包括像素的各个子集的多个不同的输入子图像，使得不同输入子图像中的像素的输入像素值在流中交错。 多个滤波器单元（92,144,206,222,238,364）以二维阵列配置连接，并且被布置为分别对各个输入子图像的输入像素值进行相应的二维 反卷积核，从而产生包括输出像素值的各个输出子图像。 多路复用器（88,332）被耦合以将输出子图像的输出像素值复用在一起以产生滤波后的输出图像。