公开(公告)号：US09048302B2

公开(公告)日：2015-06-02

申请号：US12318779

申请日：2009-01-08

Applicant: Yoshihiro Sato ,  Hiroshi Kambayashi ,  Yuki Niiyama ,  Takehiko Nomura ,  Seikoh Yoshida ,  Masayuki Iwami ,  Jiang Li

Inventor： Yoshihiro Sato ,  Hiroshi Kambayashi ,  Yuki Niiyama ,  Takehiko Nomura ,  Seikoh Yoshida ,  Masayuki Iwami ,  Jiang Li

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267

CPC classification number: H01L29/7813 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/267 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7789

Abstract: A field effect transistor has an MOS structure and is formed of a nitride based compound semiconductor. The field effect transistor includes a substrate; a semiconductor operating layer having a recess and formed on the substrate; an insulating layer formed on the semiconductor operating layer including the recess; a gate electrode formed on the insulating layer at the recess; and a source electrode and a drain electrode formed on the semiconductor operating layer with the recess in between and electrically connected to the semiconductor operating layer. The recess includes a side wall inclined relative to the semiconductor operating layer.

Abstract translation: 场效应晶体管具有MOS结构并且由氮化物基化合物半导体形成。 场效应晶体管包括衬底; 具有凹部并形成在所述基板上的半导体操作层; 形成在包括所述凹部的所述半导体操作层上的绝缘层; 在所述凹部处形成在所述绝缘层上的栅电极; 以及形成在半导体操作层上的源电极和漏电极，其中凹部位于半导体操作层之间并与半导体操作层电连接。 凹部包括相对于半导体操作层倾斜的侧壁。

公开(公告)号：US08552531B2

公开(公告)日：2013-10-08

申请号：US13180635

申请日：2011-07-12

Applicant: Masayuki Iwami

Inventor： Masayuki Iwami

IPC: H01L21/70

CPC classification number: H01L29/2003 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02581 ,  H01L21/0262 ,  H01L29/207 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872

Abstract: A nitride-based compound semiconductor includes an atom of at least one group-III element selected from the group consisting of Al, Ga, In, and B, a nitrogen atom, and a metal atom that forms a compound by bonding with an interstitial atom of the at least one group-III element. The metal atom is preferably iron or nickel. A doping concentration of the metal atom is preferably equal to a concentration of the interstitial atom of the at least one group-III element.

Abstract translation: 氮化物类化合物半导体包括选自Al，Ga，In和B中的至少一种III族元素的原子，氮原子和通过与间隙原子键合形成化合物的金属原子 的至少一个III族元素。 金属原子优选为铁或镍。 金属原子的掺杂浓度优选等于至少一种III族元素的间隙原子的浓度。

公开(公告)号：US08450782B2

公开(公告)日：2013-05-28

申请号：US13075843

申请日：2011-03-30

Applicant: Yoshihiro Sato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Takuya Kokawa ,  Masayuki Iwami ,  Sadahiro Kato

Inventor： Yoshihiro Sato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Takuya Kokawa ,  Masayuki Iwami ,  Sadahiro Kato

IPC: H01L29/76

CPC classification number: H01L29/0847 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787

Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm−3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.

Abstract translation: 场效应晶体管包括在基板上的高电阻层，形成在高电阻层上并具有碳浓度不大于1×10 18 cm -3且具有层厚度的沟道层的半导体操作层 大于10nm且不大于100nm的凹槽，形成在半导体操作层中的沟道层内部的凹部，形成在半导体操作层上的沟槽间的沟槽间的沟槽间的沟槽， 栅极绝缘膜，其形成在半导体操作层上以覆盖凹部;以及栅电极，其形成在凹部中的栅极绝缘膜上。

公开(公告)号：US08072002B2

公开(公告)日：2011-12-06

申请号：US12382941

申请日：2009-03-26

Applicant: Yuki Niyama ,  Seikoh Yoshida ,  Hiroshi Kambayashi ,  Takehiko Nomura ,  Masayuki Iwami ,  Shinya Ootomo

Inventor： Yuki Niyama ,  Seikoh Yoshida ,  Hiroshi Kambayashi ,  Takehiko Nomura ,  Masayuki Iwami ,  Shinya Ootomo

IPC: H01L29/66

CPC classification number: H01L29/2003 ,  H01L29/0843 ,  H01L29/42368 ,  H01L29/7786

Abstract: A field effect transistor formed of a semiconductor of a III group nitride compound, includes an electron running layer formed on a substrate and formed of GaN; an electron supplying layer formed on the electron running layer and formed of AlxGa1-xN (0.01≦x≦0.4), the electron supplying layer having a band gap energy different from that of the electron running layer and being separated with a recess region having a depth reaching the electron running layer; a source electrode and a drain electrode formed on the electron supplying layer with the recess region in between; a gate insulating film layer formed on the electron supplying layer for covering a surface of the electron running layer in the recess region; and a gate electrode formed on the gate insulating film layer in the recess region. The electron supplying layer has a layer thickness between 5.5 nm and 40 nm.

Abstract translation: 由III族氮化物化合物的半导体形成的场效应晶体管包括形成在衬底上并由GaN形成的电子运行层; 电子供给层，形成在电子运行层上，由Al x Ga 1-x N（0.01＆nlE; x＆nlE; 0.4）形成，电子供给层的带隙能量与电子运行层的能隙不同，并且与具有 达到电子运行层的深度; 形成在电子供给层上的源电极和漏电极，其间具有凹陷区域; 在所述电子供给层上形成的用于覆盖所述凹部的电子运行层的表面的栅极绝缘膜层; 以及形成在所述凹部区域中的所述栅极绝缘膜层上的栅电极。 电子供给层的层厚在5.5nm至40nm之间。

公开(公告)号：US20090200645A1

公开(公告)日：2009-08-13

申请号：US12364966

申请日：2009-02-03

Applicant: Takuya Kokawa ,  Sadahiro Kato ,  Yoshihiro Sato ,  Masayuki Iwami

Inventor： Takuya Kokawa ,  Sadahiro Kato ,  Yoshihiro Sato ,  Masayuki Iwami

IPC: H01L49/02

CPC classification number: H01L29/7787 ,  H01L29/045 ,  H01L29/155 ,  H01L29/2003

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate; and a semiconductor active layer formed on the buffer layer, the semiconductor active layer being formed of a nitride-based compound semiconductor, wherein: thicknesses of the first semiconductor layers in the buffer layer are non-uniform thereamong, and at least one of the first semiconductor layer has a thickness greater than a critical thickness, the critical thickness being a thickness above which a direction of warp caused by the first semiconductor layer to the substrate is inverted.

Abstract translation: 半导体电子器件包括衬底; 形成在所述基板上的缓冲层，所述缓冲层包括不少于两层的复合层，其中由氮化物基化合物半导体层形成的第一半导体层的晶格常数小于所述基板的晶格常数， 膨胀系数大于衬底的热膨胀系数，以及由具有小于第一半导体层的晶格常数的晶格常数的氮化物系化合物半导体形成的第二半导体层和大于第一半导体层的热膨胀系数的热膨胀系数 基板交替层压; 设置在所述基板和所述缓冲层之间的中间层，所述中间层由格子常数小于所述第一半导体层的晶格常数的氮化物系化合物半导体形成，所述中间层的热膨胀系数大于所述第一半导体层的热膨胀系数 基材; 以及形成在所述缓冲层上的半导体有源层，所述半导体有源层由氮化物系化合物半导体形成，其中：所述缓冲层中的所述第一半导体层的厚度不均匀，所述第一半导体层的至少一个 半导体层的厚度大于临界厚度，临界厚度是由第一半导体层向衬底引起的翘曲方向反转的厚度。

公开(公告)号：US08569800B2

公开(公告)日：2013-10-29

申请号：US13076980

申请日：2011-03-31

Applicant: Nariaki Ikeda ,  Takuya Kokawa ,  Masayuki Iwami ,  Sadahiro Kato

Inventor： Nariaki Ikeda ,  Takuya Kokawa ,  Masayuki Iwami ,  Sadahiro Kato

IPC: H01L31/072 ,  H01L31/0336

CPC classification number: H01L29/0847 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787

Abstract: A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recess.

Abstract translation: 场效应晶体管包括：形成在衬底上的缓冲层; 形成在缓冲层上的高电阻层或基底层; 形成在高电阻层或基底层上的含碳载体浓度控制层; 载体行进层，其形成在所述载流子浓度控制层上; 形成在载体行进层上的载体供给层; 由所述载体供给层形成达预定深度的凹部; 源极/漏电极，其形成在载体供给层上，其间具有凹槽; 栅极绝缘膜，形成在所述载体供给层上以覆盖所述凹部; 以及形成在凹部中的栅极绝缘膜上的栅电极。

公开(公告)号：US20130069076A1

公开(公告)日：2013-03-21

申请号：US13617156

申请日：2012-09-14

Applicant: Masayuki IWAMI ,  Takuya KOKAWA

Inventor： Masayuki IWAMI ,  Takuya KOKAWA

IPC: H01L29/205 ,  H01L21/335

CPC classification number: H01L29/7787 ,  H01L29/155 ,  H01L29/2003

Abstract: Provided is a nitride semiconductor device comprising a base substrate; a buffer layer formed above the base substrate; an active layer formed on the buffer layer; and at least two electrodes formed above the active layer. The buffer layer includes one or more composite layers that each have a plurality of nitride semiconductor layers with different lattice constants, and at least one of the one or more composite layers is doped with carbon atoms and oxygen atoms in at least a portion of a carrier region of the nitride semiconductor having the largest lattice constant among the plurality of nitride semiconductor layers, the carrier region being a region in which carriers are generated due to the difference in lattice constants between this nitride semiconductor layer and the nitride semiconductor layer formed directly thereon.

Abstract translation: 提供了一种氮化物半导体器件，其包括基底基板; 形成在所述基底基板上的缓冲层; 形成在缓冲层上的有源层; 以及形成在有源层上方的至少两个电极。 缓冲层包括一个或多个复合层，每个复合层各自具有不同晶格常数的多个氮化物半导体层，并且该一个或多个复合层中的至少一个在载体的至少一部分中掺杂有碳原子和氧原子 在多个氮化物半导体层中具有最大晶格常数的氮化物半导体的区域，由于该氮化物半导体层和直接形成的氮化物半导体层之间的晶格常数的差异，载流子区域是其中产生载流子的区域。

公开(公告)号：US08338859B2

公开(公告)日：2012-12-25

申请号：US12569429

申请日：2009-09-29

Applicant: Takuya Kokawa ,  Sadahiro Kato ,  Yoshihiro Sato ,  Masayuki Iwami

Inventor： Takuya Kokawa ,  Sadahiro Kato ,  Yoshihiro Sato ,  Masayuki Iwami

IPC: H01L21/02 ,  H01L21/338

CPC classification number: H01L29/7783 ,  H01L29/2003 ,  H01L29/66462

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and smaller coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area to the upper layer area is bent at said boundary surface.

Abstract translation: 半导体电子器件包括衬底; 形成在所述基板上的缓冲层，具有两层或多层复合层，其中第一半导体层包含氮化物基化合物半导体，该氮化物基化合物半导体具有比基板更小的晶格常数和更大的热膨胀系数，第二半导体层包括氮化物基化合物半导体 具有比第一半导体层更小的晶格常数和较小的热膨胀系数交替层压; 半导体工作层，包括形成在所述缓冲层上的氮化物基化合物半导体; 形成在直接位于所述缓冲层下方的位置与所述半导体工作层的内部区域之间的位置处的氮化物基化合物半导体的位错降低层，并且包括具有不均匀边界面的下层区域和上层区域，其中， 从所述下层区延伸到所述上层区域的穿透位错在所述边界面弯曲。

公开(公告)号：US08067787B2

公开(公告)日：2011-11-29

申请号：US12364966

申请日：2009-02-03

Applicant: Takuya Kokawa ,  Sadahiro Kato ,  Yoshihiro Sato ,  Masayuki Iwami

Inventor： Takuya Kokawa ,  Sadahiro Kato ,  Yoshihiro Sato ,  Masayuki Iwami

IPC: H01L21/02

CPC classification number: H01L29/7787 ,  H01L29/045 ,  H01L29/155 ,  H01L29/2003

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate; and a semiconductor active layer formed on the buffer layer, the semiconductor active layer being formed of a nitride-based compound semiconductor, wherein: thicknesses of the first semiconductor layers in the buffer layer are non-uniform thereamong, and at least one of the first semiconductor layer has a thickness greater than a critical thickness, the critical thickness being a thickness above which a direction of warp caused by the first semiconductor layer to the substrate is inverted.

Abstract translation: 半导体电子器件包括衬底; 形成在所述基板上的缓冲层，所述缓冲层包括不少于两层的复合层，其中由氮化物基化合物半导体层形成的第一半导体层的晶格常数小于所述基板的晶格常数， 膨胀系数大于衬底的热膨胀系数，以及由具有小于第一半导体层的晶格常数的晶格常数的氮化物系化合物半导体形成的第二半导体层和大于第一半导体层的热膨胀系数的热膨胀系数 基板交替层压; 设置在所述基板和所述缓冲层之间的中间层，所述中间层由格子常数小于所述第一半导体层的晶格常数的氮化物系化合物半导体形成，所述中间层的热膨胀系数大于所述第一半导体层的热膨胀系数 基材; 以及形成在所述缓冲层上的半导体有源层，所述半导体有源层由氮化物系化合物半导体形成，其中：所述缓冲层中的所述第一半导体层的厚度不均匀，所述第一半导体层的至少一个 半导体层的厚度大于临界厚度，临界厚度是由第一半导体层向衬底引起的翘曲方向反转的厚度。

公开(公告)号：US06898224B2

公开(公告)日：2005-05-24

申请号：US10219093

申请日：2002-08-13

Applicant: Mikihiro Yokozeki ,  Kaname Saito ,  Hirotatsu Ishii ,  Masayuki Iwami

Inventor： Mikihiro Yokozeki ,  Kaname Saito ,  Hirotatsu Ishii ,  Masayuki Iwami

IPC: H01S3/067 ,  H01S5/028 ,  H01S5/22 ,  H01S5/34 ,  H01S5/343 ,  H01S5/00

CPC classification number: B82Y20/00 ,  H01S3/06766 ,  H01S3/06775 ,  H01S5/0021 ,  H01S5/02284 ,  H01S5/02438 ,  H01S5/028 ,  H01S5/0282 ,  H01S5/146 ,  H01S5/2036 ,  H01S5/22 ,  H01S5/3413 ,  H01S5/34306 ,  H01S2304/04

Abstract: Disclosed are semiconductor laser devices which hardly have degradation when used to generate high power of 200 mW or greater over a long period of time. An exemplary semiconductor laser device comprising a semiconductor substrate, and a layer structure formed on the semiconductor substrate and having an active layer with a quantum well layer formed of a ternary system mixed crystal of a III-V compound semiconductor. The material of the quantum well layer is formed in an equilibrium phase which is thermodynamically stable at both the growth temperature and the operating temperature. The material preferably has a substantially homogeneous disordered microstructure. In a preferred embodiment, the material comprises GaAsSb. The quantum well layer exhibits improved thermodynamic stability, and the device can emit light in the 980 nm band at high power levels for longer periods of time without failure in comparison to conventional InGaAs 980 nm pumping lasers.

Abstract translation: 公开了当用于在长时间内产生200mW或更大的大功率时几乎不劣化的半导体激光器件。 一种示例性的半导体激光器件，包括半导体衬底和形成在半导体衬底上并且具有由III-V族化合物半导体的三元系混合晶形成的量子阱层的有源层的层结构。 量子阱层的材料形成在平衡相，在生长温度和工作温度下都是热力学稳定的。 该材料优选具有基本均匀的无序微结构。 在优选实施例中，该材料包括GaAsSb。 量子阱层表现出改进的热力学稳定性，器件可以在高功率水平下在980nm波段内发射较长时间的光，而与常规的InGaAs 980nm泵浦激光器相比，可以不发生故障。