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1.发明授权公开(公告)号：US08341380B2
公开(公告)日：2012-12-25
申请号：US12851483
申请日：2010-08-05
申请人： James Leroy Deming , Mark Allen Mosley , William Craig McKnight , Emmett M. Kilgrariff , Steven E. Molnar , Colyn Scott Case
发明人： James Leroy Deming , Mark Allen Mosley , William Craig McKnight , Emmett M. Kilgrariff , Steven E. Molnar , Colyn Scott Case
CPC分类号： G06F12/1027 , G06F2212/401 , G06F2212/652 , G06F2212/684
摘要： One embodiment of the present invention sets forth a system and method for supporting high-throughput virtual to physical address translation using compressed TLB cache lines with variable address range coverage. The amount of memory covered by a TLB cache line depends on the page size and page table entry (PTE) compression level. When a TLB miss occurs, a cache line is allocated with an assumed address range that may be larger or smaller than the address range of the PTE data actually returned. Subsequent requests that hit a cache line with a fill pending are queued until the fill completes. When the fill completes, the cache line's address range is set to the address range of the PTE data returned. Queued requests are replayed and any that fall outside the actual address range are reissued, potentially generating additional misses and fills.
摘要翻译： 本发明的一个实施例阐述了一种使用具有可变地址范围覆盖的压缩TLB高速缓存行来支持高吞吐量虚拟到物理地址转换的系统和方法。 TLB缓存行覆盖的内存量取决于页面大小和页表项（PTE）压缩级别。 当发生TLB未命中时，分配具有可能大于或小于实际返回的PTE数据的地址范围的假定地址范围的高速缓存行。 后续请求命中一个填充待处理的缓存行排队等待填充完成。 当填充完成时，缓存行的地址范围设置为返回的PTE数据的地址范围。 排队的请求被重播，任何落在实际地址范围之外的任何地址将被重新发布，潜在地产生额外的未命中和填充。
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2.发明申请公开(公告)号：US20110072235A1
公开(公告)日：2011-03-24
申请号：US12851483
申请日：2010-08-05
申请人： James Leroy Deming , Mark Allen Mosley , William Craig McKnight , Emmett M. Kilgrariff , Steven E. Molnar , Colyn Scott Case
发明人： James Leroy Deming , Mark Allen Mosley , William Craig McKnight , Emmett M. Kilgrariff , Steven E. Molnar , Colyn Scott Case
CPC分类号： G06F12/1027 , G06F2212/401 , G06F2212/652 , G06F2212/684
摘要： One embodiment of the present invention sets forth a system and method for supporting high-throughput virtual to physical address translation using compressed TLB cache lines with variable address range coverage. The amount of memory covered by a TLB cache line depends on the page size and page table entry (PTE) compression level. When a TLB miss occurs, a cache line is allocated with an assumed address range that may be larger or smaller than the address range of the PTE data actually returned. Subsequent requests that hit a cache line with a fill pending are queued until the fill completes. When the fill completes, the cache line's address range is set to the address range of the PTE data returned. Queued requests are replayed and any that fall outside the actual address range are reissued, potentially generating additional misses and fills.
摘要翻译： 本发明的一个实施例阐述了一种使用具有可变地址范围覆盖的压缩TLB高速缓存行来支持高吞吐量虚拟到物理地址转换的系统和方法。 TLB缓存行覆盖的内存量取决于页面大小和页表项（PTE）压缩级别。 当发生TLB未命中时，分配具有可能大于或小于实际返回的PTE数据的地址范围的假定地址范围的高速缓存行。 后续请求命中一个填充待处理的缓存行排队等待填充完成。 当填充完成时，缓存行的地址范围设置为返回的PTE数据的地址范围。 排队的请求被重播，任何落在实际地址范围之外的任何地址将被重新发布，潜在地产生额外的未命中和填充。
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公开(公告)号：US09569348B1
公开(公告)日：2017-02-14
申请号：US12842876
申请日：2010-07-23
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0811 , G06F12/0813 , G06F12/0862 , G06F12/0875 , G06F12/10 , G06F12/1009 , G06F12/1027 , G06F12/12 , G06F2212/1044 , G06F2212/401 , G06F2212/6026 , G06F2212/681 , G06F2212/684
摘要： One embodiment of the present invention sets forth a technique for performing a method for compressing page table entries (PTEs) prior to storing the PTEs in a translation look-aside buffer (TLB). A page table entry (PTE) request is received for a PTE that is not stored in the TLB. The PTE as well as a plurality of PTEs that are adjacent to the PTE are retrieved from a memory. The PTE and the plurality of PTEs are compressed and then stored in the TLB.
摘要翻译： 本发明的一个实施例提出了一种用于在将PTE存储在转换后备缓冲器（TLB）之前执行用于压缩页表条目（PTE）的方法的技术。 接收到未存储在TLB中的PTE的页表项（PTE）请求。 从存储器中检索PTE以及与PTE相邻的多个PTE。 PTE和多个PTE被压缩，然后存储在TLB中。
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