公开(公告)号：US20120178237A1

公开(公告)日：2012-07-12

申请号：US13418994

申请日：2012-03-13

Applicant: Charles W. Koburger, III ,  Peter Zeitzoff ,  Mariko Takayanagi

Inventor： Charles W. Koburger, III ,  Peter Zeitzoff ,  Mariko Takayanagi

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/823878 ,  H01L27/0921

Abstract: A method of forming a semiconductor device includes defining a first type region and a second type region in a substrate, t separated by one or more inter-well STI structures; etching and filling, in at least one of the first type region and the second type region, one or more intra-well STI structures for isolating semiconductor devices formed within a same polarity well, wherein the one or more inter-well STI structures are formed at a substantially same depth with respect to the one or more intra-well STI structures; implanting, a main well region, wherein a bottom of the main well region is disposed above a bottom of the one or more inter-well and intra-well STI features; and implanting, one or more deep well regions that couple main well regions, wherein the one or more deep well regions are spaced away from the one or more inter-well STI structures.

Abstract translation: 一种形成半导体器件的方法包括：在衬底中限定由一个或多个阱间STI结构分离的第一类型区域和第二类型区域; 蚀刻和填充在第一类型区域和第二类型区域中的至少一个区域中的一个或多个井下STI结构，用于隔离在相同极性阱内形成的半导体器件，其中形成一个或多个阱间STI结构 相对于一个或多个井内STI结构基本相同的深度; 植入，主井区，其中主井区的底部设置在所述一个或多个井间和井内STI特征的底部之上; 以及植入，连接主井区域的一个或多个深井区域，其中所述一个或多个深井区域与所述一个或多个井间STI结构间隔开。

公开(公告)号：US08134209B2

公开(公告)日：2012-03-13

申请号：US12640658

申请日：2009-12-17

Applicant: Atsushi Yagishita ,  Makoto Fujiwara ,  Hirohisa Kawasaki ,  Mariko Takayanagi

Inventor： Atsushi Yagishita ,  Makoto Fujiwara ,  Hirohisa Kawasaki ,  Mariko Takayanagi

IPC: H01L27/12

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

Abstract: Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.

Abstract translation: 提供多栅极金属氧化物硅晶体管和制造多栅极金属氧化物硅晶体管的方法。 多栅极金属氧化物硅晶体管包含在浅沟槽区域之间包含一个或多个凸部的体硅衬底; 一个或多个在凸部上的电介质部分; 电介质部分上的一个或多个硅散热片; 在浅沟槽隔离区域的浅沟槽隔离层; 和栅电极。 浅沟槽隔离层的上表面可以位于凸部的上表面下方，或者浅沟槽隔离层的上表面可以位于第一介电层的下表面和上表面之间。 多栅极金属氧化物硅晶体管可以包含与源极/漏极区域中的凸部的侧表面相邻的第二间隔物。

公开(公告)号：US20110251281A1

公开(公告)日：2011-10-13

申请号：US13060532

申请日：2009-09-08

Applicant: Tetsushi Taguchi ,  Mariko Takayanagi

Inventor： Tetsushi Taguchi ,  Mariko Takayanagi

IPC: A61K31/196 ,  A61P7/02

CPC classification number: A61L31/042 ,  C08K5/0008 ,  C08K5/09 ,  C08L5/00 ,  C08L5/08 ,  C08L5/10 ,  C08L89/00 ,  C08L89/04 ,  C08L89/06

Abstract: Previously reported composite materials comprising a hydrophilic high-molecular-weight matrix and a low-molecular-weight organic compound involve a problem in that: it is difficult to compound a high load of the low-molecular-weight organic compound in the high-molecular-weight matrix; and thus produced composite material yields a high-molecular-weight matrix component that can form a thrombus when contacting with blood. Now, it becomes possible to produce a composite material having an antithrombogenic activity and a high content of a low-molecular-weight organic compound by the present invention comprising the steps of: crosslinking a polymer with an organic acid derivative which is used as a crosslinker in an organic solvent while at the same time embedding the low-molecular-weight organic compound therein; and substituting the organic solvent by water after the production of the high-molecular-weight matrix to effect precipitation and compounding of the low-molecular-weight organic compound in the high-molecular-weight matrix.

Abstract translation: 以前报道的包含亲水性高分子量基质和低分子量有机化合物的复合材料存在以下问题：难以将高分子量有机化合物在高分子量 重量矩阵; 从而产生复合材料产生当与血液接触时可形成血栓的高分子量基质组分。 现在，可以通过本发明制备具有抗血栓形成活性和高含量的低分子量有机化合物的复合材料，包括以下步骤：用用作交联剂的有机酸衍生物交联聚合物 在有机溶剂中同时在其中包埋低分子量有机化合物; 在生成高分子量基质后用水代替有机溶剂，使高分子量基质中的低分子量有机化合物发生沉淀和配混。

公开(公告)号：US07944004B2

公开(公告)日：2011-05-17

申请号：US12411425

申请日：2009-03-26

Applicant: Mariko Takayanagi

Inventor： Mariko Takayanagi

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve forming a layer of high-K atoms over a conventional gate dielectric and heating the layer of high-K atoms to form a high-K gate dielectric layer. Methods of suppressing gate leakage current while mitigating mobility degradation are also described.

Abstract translation: 公开了制造具有多个厚度和/或多个组成的高K栅极电介质层的集成电路和包含多个厚度和/或多个组成的高K栅极电介质的集成电路的方法。 所述方法包括在常规栅极电介质上形成高K原子层，并加热高K原子层以形成高K栅极电介质层。 还描述了抑制栅极泄漏电流同时减轻迁移率降低的方法。

公开(公告)号：US20100244207A1

公开(公告)日：2010-09-30

申请号：US12411425

申请日：2009-03-26

Applicant: Mariko Takayanagi

Inventor： Mariko Takayanagi

IPC: H01L23/58 ,  H01L21/469

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve forming a layer of high-K atoms over a conventional gate dielectric and heating the layer of high-K atoms to form a high-K gate dielectric layer. Methods of suppressing gate leakage current while mitigating mobility degradation are also described.

Abstract translation: 公开了制造具有多个厚度和/或多个组成的高K栅极电介质层的集成电路和包含多个厚度和/或多个组成的高K栅极电介质的集成电路的方法。 所述方法包括在常规栅极电介质上形成高K原子层，并加热高K原子层以形成高K栅极电介质层。 还描述了抑制栅极泄漏电流同时减轻迁移率降低的方法。

公开(公告)号：US07696585B2

公开(公告)日：2010-04-13

申请号：US11933845

申请日：2007-11-01

Applicant: Mariko Takayanagi

Inventor： Mariko Takayanagi

IPC: H01L29/76

CPC classification number: H01L21/28097 ,  H01L21/28026 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; a first gate dielectric layer provided on the semiconductor substrate, the relative dielectric constant ratio of the first gate dielectric layer being no less than 8; a second gate dielectric layer provided on the semiconductor substrate, the relative dielectric constant ratio of the second gate dielectric layer being no less than 8; a first gate electrode provided on the first gate dielectric layer and made of germanide which is a metallic compound containing a metal element of a rare earth metal; and a second gate electrode provided on the second gate dielectric layer and made of silicide which is a metallic compound containing the same metal element of a rare earth metal as the germanide in the first gate electrode.

Abstract translation: 在本发明的一个方面，半导体器件可以包括半导体衬底; 设置在所述半导体衬底上的第一栅介质层，所述第一栅介质层的相对介电常数比不小于8; 设置在所述半导体衬底上的第二栅介质层，所述第二栅介质层的相对介电常数比不小于8; 第一栅电极，设置在第一栅极电介质层上并由锗化物制成，其是含有稀土金属的金属元素的金属化合物; 以及设置在第二栅极电介质层上并由硅化物制成的第二栅极电极，其是在第一栅电极中含有与锗化物相同的稀土金属的金属元素的金属化合物。

公开(公告)号：US20080203498A1

公开(公告)日：2008-08-28

申请号：US11933845

申请日：2007-11-01

Applicant: Mariko TAKAYANAGI

Inventor： Mariko TAKAYANAGI

IPC: H01L29/78

CPC classification number: H01L21/28097 ,  H01L21/28026 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; a first gate dielectric layer provided on the semiconductor substrate, the relative dielectric constant ratio of the first gate dielectric layer being no less than 8; a second gate dielectric layer provided on the semiconductor substrate, the relative dielectric constant ratio of the second gate dielectric layer being no less than 8; a first gate electrode provided on the first gate dielectric layer and made of germanide which is a metallic compound containing a metal element of a rare earth metal; and a second gate electrode provided on the second gate dielectric layer and made of silicide which is a metallic compound containing the same metal element of a rare earth metal as the germanide in the first gate electrode.

Abstract translation: 在本发明的一个方面，半导体器件可以包括半导体衬底; 设置在所述半导体衬底上的第一栅介质层，所述第一栅介质层的相对介电常数比不小于8; 设置在所述半导体衬底上的第二栅介质层，所述第二栅介质层的相对介电常数比不小于8; 第一栅电极，设置在第一栅极电介质层上并由锗化物制成，其是含有稀土金属的金属元素的金属化合物; 以及设置在第二栅极电介质层上并由硅化物制成的第二栅极电极，其是在第一栅电极中含有与锗化物相同的稀土金属的金属元素的金属化合物。

公开(公告)号：US20050064667A1

公开(公告)日：2005-03-24

申请号：US10941814

申请日：2004-09-16

Applicant: Daisuke Matsushita ,  Koichi Muraoka ,  Seiji Inumiya ,  Koichi Kato ,  Kazuhiro Eguchi ,  Mariko Takayanagi ,  Yasushi Nakasaki

Inventor： Daisuke Matsushita ,  Koichi Muraoka ,  Seiji Inumiya ,  Koichi Kato ,  Kazuhiro Eguchi ,  Mariko Takayanagi ,  Yasushi Nakasaki

IPC: H01L21/318 ,  H01L21/00 ,  H01L21/28 ,  H01L21/314 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/84 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28202 ,  H01L21/022 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device manufacturing method comprises: forming a first nitride film on a semiconductor substrate; forming a first oxide film between said semiconductor substrate and said nitride film and forming a second oxide film on said nitride film; forming a second nitride film or an oxide and nitride film on said first nitride film by nitriding said second oxide film; and forming a gate electrode on a gate insulative film including said first oxide film, said first nitride film, and said second nitride film or said oxide and nitride film.

Abstract translation: 半导体器件制造方法包括：在半导体衬底上形成第一氮化物膜; 在所述半导体衬底和所述氮化物膜之间形成第一氧化物膜，并在所述氮化膜上形成第二氧化膜; 通过氮化所述第二氧化物膜在所述第一氮化物膜上形成第二氮化物膜或氧化物和氮化物膜; 以及在包括所述第一氧化物膜，所述第一氮化物膜和所述第二氮化物膜或所述氧化物和氮化物膜的栅极绝缘膜上形成栅电极。

公开(公告)号：US06664577B2

公开(公告)日：2003-12-16

申请号：US10106345

申请日：2002-03-27

Applicant: Mariko Takayanagi

Inventor： Mariko Takayanagi

IPC: H01L2976

CPC classification number: H01L21/823462 ,  C23C16/401 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/45531 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31608 ,  H01L21/31645 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor device comprising a semiconductor substrate and a MOSFET provided on the semiconductor substrate, the MOSFET including a gate insulating film and a gate electrode provided on the gate insulating film, wherein the gate insulating film has a higher dielectric constant in a side contacting the semiconductor substrate than in a side contacting the gate electrode.

Abstract translation: 一种半导体器件，包括半导体衬底和设置在半导体衬底上的MOSFET，所述MOSFET包括栅极绝缘膜和设置在栅极绝缘膜上的栅电极，其中栅极绝缘膜在与半导体接触的一侧具有较高的介电常数 衬底，而不是在与栅电极接触的一侧。

公开(公告)号：US20110147839A1

公开(公告)日：2011-06-23

申请号：US12640658

申请日：2009-12-17

Applicant: Atsushi Yagishita ,  Makoto Fujiwara ,  Hirohisa Kawasaki ,  Mariko Takayanagi

Inventor： Atsushi Yagishita ,  Makoto Fujiwara ,  Hirohisa Kawasaki ,  Mariko Takayanagi

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

Abstract: Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.

Abstract translation: 提供多栅极金属氧化物硅晶体管和制造多栅极金属氧化物硅晶体管的方法。 多栅极金属氧化物硅晶体管包含在浅沟槽区域之间包含一个或多个凸部的体硅衬底; 一个或多个在凸部上的电介质部分; 电介质部分上的一个或多个硅散热片; 在浅沟槽隔离区域的浅沟槽隔离层; 和栅电极。 浅沟槽隔离层的上表面可以位于凸部的上表面下方，或者浅沟槽隔离层的上表面可以位于第一介电层的下表面和上表面之间。 多栅极金属氧化物硅晶体管可以包含与源极/漏极区域中的凸部的侧表面相邻的第二间隔物。