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    Method to form a robust TiCI4 based CVD TiN film
    1.
    发明申请
    Method to form a robust TiCI4 based CVD TiN film 审中-公开
    形成坚固的TiCI4基CVD TiN膜的方法

    公开(公告)号：US20050112876A1

    公开(公告)日：2005-05-26

    申请号：US10723237

    申请日：2003-11-26

    申请人： Chih-Ta Wu ,  Kuo Yin Lin ,  Min-Hsiung Chiang

    发明人： Chih-Ta Wu ,  Kuo Yin Lin ,  Min-Hsiung Chiang

    IPC分类号： C23C16/34 ,  C23C16/56 ,  H01L21/20 ,  H01L21/768

    CPC分类号： C23C16/56 ,  C23C16/34 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862

    摘要： A method is described for a plasma treatment of a TiCl4 based CVD deposited TiN layer that reduces stress, lowers resistivity, and improves film stability. Resistivity is stable in an air ambient for up to 48 hours after the plasma treatment. A TiN layer is treated with a N-containing plasma that includes N2, NH3, or N2H4 at a temperature between 500° C. and 700° C. Optionally, H2 may be added to N2 in the plasma step which removes chloride impurities and densifies the TiN layer. The TiN layer may serve as a barrier layer, an ARC layer, or as a bottom electrode in a MIM capacitor. An improved resistance of the treated TiN layer to oxidation during formation of an oxide based insulator layer and a lower leakage current in the MIM capacitor is also achieved.

    摘要翻译： 描述了一种用于等离子体处理基于TiCl 4的CVD沉积TiN层的方法，其降低应力，降低电阻率并提高膜的稳定性。 等离子体处理后电阻率在空气环境中稳定长达48小时。 用含N的等离子体处理TiN层，该等离子体包括N 2，NH 3或N 2 H 4， 在500℃至700℃之间的温度下，可以在等离子体步骤中将H 2 N加入到N 2 N中，除去氯化物杂质并致密化 TiN层。 TiN层可以用作MIM电容器中的阻挡层，ARC层或底电极。 还实现了在形成氧化物基绝缘体层期间处理的TiN层对氧化的改善的电阻和MIM电容器中较低的漏电流。

    Method of forming MIM capacitor electrodes
    2.
    发明申请
    Method of forming MIM capacitor electrodes 有权
    形成MIM电容器电极的方法

    公开(公告)号：US20050215004A1

    公开(公告)日：2005-09-29

    申请号：US10811657

    申请日：2004-03-29

    申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    IPC分类号： H01G4/005 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L23/522 ,  H01L29/06

    CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

    摘要翻译： 公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。 该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能， 在MIM电容器的制造中。 该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉​​积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

    Semiconductor device having hydrogen-containing layer
    4.
    发明授权
    Semiconductor device having hydrogen-containing layer 有权
    具有含氢层的半导体装置

    公开(公告)号：US07786552B2

    公开(公告)日：2010-08-31

    申请号：US11149575

    申请日：2005-06-10

    申请人： Tsung-Hsun Huang ,  Kuo-Yin Lin ,  Chung-Yi Yu ,  Chih-Ta Wu ,  Chia-Shiung Tsai

    发明人： Tsung-Hsun Huang ,  Kuo-Yin Lin ,  Chung-Yi Yu ,  Chih-Ta Wu ,  Chia-Shiung Tsai

    IPC分类号： H01L23/58

    CPC分类号： H01L21/76829 ,  H01L21/3003 ,  H01L21/3105 ,  H01L21/3143 ,  H01L21/76828

    摘要： A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and the hydrogen-containing layer. The hydrogen atoms of the hydrogen-containing layer are introduced into the dielectric layers without being blocked by the silicon nitride layer, thereby reducing leakage current therein.

    摘要翻译： 公开了一种用于减小半导体结构中的漏电流的方法。 一个或多个电介质层形成在半导体衬底上，其上构造有至少一个器件。 在电介质层上形成含氢层。 氮化硅钝化层覆盖电介质层和含氢层。 含氢层的氢原子被引入到电介质层中而不被氮化硅层阻挡，从而减少其中的漏电流。

    Method of forming MIM capacitor electrodes
    5.
    发明授权
    Method of forming MIM capacitor electrodes 有权
    形成MIM电容器电极的方法

    公开(公告)号：US07199001B2

    公开(公告)日：2007-04-03

    申请号：US10811657

    申请日：2004-03-29

    申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

    摘要翻译： 公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。 该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能， 在MIM电容器的制造中。 该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉​​积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

    Methods to improve photonic performances of photo-sensitive integrated circuits
    6.
    发明授权
    Methods to improve photonic performances of photo-sensitive integrated circuits 有权
    提高光敏集成电路光子性能的方法

    公开(公告)号：US07189957B2

    公开(公告)日：2007-03-13

    申请号：US10906604

    申请日：2005-02-25

    申请人： Shih-Chi Fu ,  Yuan-Hung Liu ,  Kuo-Yin Lin ,  Feng-Jia Shiu ,  Chia-Shiung Tsai ,  Ching-Sen Kuo ,  Jieh-Jang Chen

    发明人： Shih-Chi Fu ,  Yuan-Hung Liu ,  Kuo-Yin Lin ,  Feng-Jia Shiu ,  Chia-Shiung Tsai ,  Ching-Sen Kuo ,  Jieh-Jang Chen

    IPC分类号： H01L31/00 ,  H01L21/00

    CPC分类号： H01L27/14685 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/14654

    摘要： Described is a light-directing feature formed in the inter-level dielectric (ILD) layer in combination with an anti-reflective (AR) layer to effectively and simultaneously increase quantum efficiency and cross-talk immunity thereby improving photonic performances of photo-sensitive integrated circuits. A plurality of photosensor cells is formed on a semiconductor substrate. An AR layer is subsequently formed on the plurality of photosensor cells, the AR layer being substantially non-reflective of incident light. An ILD layer is then formed over the AR layer, the ILD layer comprising a plurality of light-directing features formed in openings in the ILD layer over the AR layer above and about certain of the plurality of photosensor cells.

    摘要翻译： 描述了在层间电介质（ILD）层中形成的与抗反射（AR）层组合的光导特征，以有效并同时地提高量子效率和串扰抗扰度，从而改善光敏集成的光子性能 电路。 多个光电传感器单元形成在半导体基板上。 随后在多个光电传感器单元上​​形成AR层，AR层基本上不反射入射光。 然后在AR层上形成ILD层，ILD层包括多个导光特征，其形成在ILD层中的多个光敏元件上方和周围的AR层上的开口中。

    Atomic layer deposition (ALD) method with enhanced deposition rate
    7.
    发明授权
    Atomic layer deposition (ALD) method with enhanced deposition rate 有权
    原子层沉积（ALD）方法具有提高的沉积速率

    公开(公告)号：US07169713B2

    公开(公告)日：2007-01-30

    申请号：US10672778

    申请日：2003-09-26

    申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Chia-Shiung Tsai

    发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Chia-Shiung Tsai

    IPC分类号： H01L21/31

    CPC分类号： H01L21/0228 ,  C23C16/45527 ,  H01L21/3141

    摘要： An atomic layer deposition method for forming a microelectronic layer employs a reactor chamber pressure of greater than about 500 mtorr and more preferably from about 20 to about 50 torr. By employing a reactor chamber pressure within the foregoing range, the microelectronic layer is formed with an enhanced deposition rate while employing the atomic layer deposition method, due to a gas phase chemical vapor deposition component to the atomic layer deposition method.

    摘要翻译： 用于形成微电子层的原子层沉积方法采用的反应器室压力大于约500mtorr，更优选为约20至约50托。 通过采用上述范围内的反应室压力，由于采用原子层沉积方法的气相化学气相沉积成分，由于采用原子层沉积法，所以微电子层以增加的沉积速率形成。

    SYSTEM AND METHOD FOR OPERATING CHEMICAL MECHANICAL POLISHING PROCESS
    8.
    发明申请
    SYSTEM AND METHOD FOR OPERATING CHEMICAL MECHANICAL POLISHING PROCESS 审中-公开
    操作化学机械抛光工艺的系统和方法

    公开(公告)号：US20140053980A1

    公开(公告)日：2014-02-27

    申请号：US13591167

    申请日：2012-08-21

    申请人： Chih-I Peng ,  Hsiang-Pi Chang ,  Cary Chia-Chiung Lo ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Chih-Yuan Yang

    发明人： Chih-I Peng ,  Hsiang-Pi Chang ,  Cary Chia-Chiung Lo ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Chih-Yuan Yang

    IPC分类号： B01D53/26 ,  B44C1/22

    CPC分类号： B01D53/265

    摘要： A chemical mechanical polishing (CMP) chamber is disclosed. The CMP chamber includes a chamber body, a door mounted on the chamber body and a chamber substructure being one selected from a group consisting of a moisture separator separating a moisture generated in the CMP chamber, a supplementary exhaust port, a transparent window mounted on the door, a sampling port mounted on the door, a sealing material including a metal frame, an o-ring for sealing the door and a combination thereof.

    摘要翻译： 公开了一种化学机械抛光（CMP）室。 CMP室包括室主体，安装在室主体上的门和一个室底部结构，其中一个选自一个选自由分离在CMP室中产生的水分的湿气分离器组成的组，辅助排气口，安装在该室主体上的透明窗口 门，安装在门上的取样口，包括金属框架的密封材料，用于密封门的O形环及其组合。

    Methods to Improve Photonic Performances of Photo-Sensitive Integrated Circuits
    9.
    发明申请
    Methods to Improve Photonic Performances of Photo-Sensitive Integrated Circuits 有权
    提高光敏集成电路光子性能的方法

    公开(公告)号：US20060192083A1

    公开(公告)日：2006-08-31

    申请号：US10906604

    申请日：2005-02-25

    申请人： Shih-Chi Fu ,  Yuan-Hung Liu ,  Kuo-Yin Lin ,  Feng-Jia Shiu ,  Chia-Shiung Tsai ,  Ching-Sen Kuo ,  Jieh-Jang Chen

    发明人： Shih-Chi Fu ,  Yuan-Hung Liu ,  Kuo-Yin Lin ,  Feng-Jia Shiu ,  Chia-Shiung Tsai ,  Ching-Sen Kuo ,  Jieh-Jang Chen

    IPC分类号： H01L27/00 ,  H01L31/00

    CPC分类号： H01L27/14685 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/14654

    摘要： Described is a light-directing feature formed in the inter-level dielectric (ILD) layer in combination with an anti-reflective (AR) layer to effectively and simultaneously increase quantum efficiency and cross-talk immunity thereby improving photonic performances of photo-sensitive integrated circuits. A plurality of photosensor cells is formed on a semiconductor substrate. An AR layer is subsequently formed on the plurality of photosensor cells, the AR layer being substantially non-reflective of incident light. An ILD layer is then formed over the AR layer, the ILD layer comprising a plurality of light-directing features formed in openings in the ILD layer over the AR layer above and about certain of the plurality of photosensor cells.

    摘要翻译： 描述了在层间电介质（ILD）层中形成的与抗反射（AR）层组合的光导特征，以有效并同时地提高量子效率和串扰抗扰度，从而改善光敏集成的光子性能 电路。 多个光电传感器单元形成在半导体基板上。 随后在多个光电传感器单元上​​形成AR层，AR层基本上不反射入射光。 然后在AR层上形成ILD层，ILD层包括多个导光特征，其形成在ILD层中的多个光敏元件上方和周围的AR层上的开口中。