公开(公告)号：USRE41697E1

公开(公告)日：2010-09-14

申请号：US11235648

申请日：2005-09-26

Applicant: Chia-Tung Ho ,  Feng-Jia Shih ,  Jieh-Jang Chen ,  Ching-Sen Kuo ,  Shih-Chi Fu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

Inventor： Chia-Tung Ho ,  Feng-Jia Shih ,  Jieh-Jang Chen ,  Ching-Sen Kuo ,  Shih-Chi Fu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  G03F7/0035 ,  G03F7/09 ,  G03F7/16 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate and baked at or slightly above its Tg so that it reflows and fills the holes. The photoresist is exposed without a mask at a dose that allows the developer to thin the photoresist to a recessed depth within the holes. After the photoresist is hardened with a 250° C. bake, a second photoresist is coated on the substrate to form a planarized film with a thickness variation of less than 50 Angstroms between low and high duty ratio hole regions. One application is where the second photoresist is used to form a trench pattern in a via first dual damascene method. Secondly, the method is useful in fabricating MIM capacitors.

Abstract translation: 描述了在具有不同占空比的孔的基板上形成平坦化光致抗蚀剂涂层的方法。 优选将包含酚醛清漆树脂和重氮萘醌光敏化合物的第一光致抗蚀剂涂覆在基材上并在其Tg以上或略高于其Tg的温度下使其回流并填充孔。 以允许显影剂将光致抗蚀剂减薄到孔内的凹陷深度的剂量，光刻胶不用掩模曝光。 在250℃烘烤后光致抗蚀剂硬化后，在基板上涂覆第二光致抗蚀剂，以形成厚度变化小于50埃的低和高占空比孔区域的平坦化膜。 一种应用是第二光致抗蚀剂用于以通孔第一双镶嵌方法形成沟槽图案。 其次，该方法在制造MIM电容器方面是有用的。

公开(公告)号：US06645851B1

公开(公告)日：2003-11-11

申请号：US10245429

申请日：2002-09-17

Applicant: Chia-Tung Ho ,  Feng-Jia Shih ,  Jieh-Jang Chen ,  Ching-Sen Kuo ,  Shih-Chi Fu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsia

Inventor： Chia-Tung Ho ,  Feng-Jia Shih ,  Jieh-Jang Chen ,  Ching-Sen Kuo ,  Shih-Chi Fu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsia

IPC: H01L214763

CPC classification number: H01L21/76808 ,  G03F7/0035 ,  G03F7/09 ,  G03F7/16 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate and baked at or slightly above its Tg so that it reflows and fills the holes. The photoresist is exposed without a mask at a dose that allows the developer to thin the photoresist to a recessed depth within the holes. After the photoresist is hardened with a 250° C. bake, a second photoresist is coated on the substrate to form a planarized film with a thickness variation of less than 50 Angstroms between low and high duty ratio hole regions. One application is where the second photoresist is used to form a trench pattern in a via first dual damascene method. Secondly, the method is useful in fabricating MIM capacitors.

Abstract translation: 描述了在具有不同占空比的孔的基板上形成平坦化光致抗蚀剂涂层的方法。 优选将包含酚醛清漆树脂和重氮萘醌光敏化合物的第一光致抗蚀剂涂覆在基材上并在其Tg以上或略高于其Tg的温度下使其回流并填充孔。 以允许显影剂将光致抗蚀剂减薄到孔内的凹陷深度的剂量，光刻胶不用掩模曝光。 在250℃烘烤后光致抗蚀剂硬化后，在基板上涂覆第二光致抗蚀剂，以形成厚度变化小于50埃的低和高占空比孔区域的平坦化膜。 一种应用是第二光致抗蚀剂用于以通孔第一双镶嵌方法形成沟槽图案。 其次，该方法在制造MIM电容器方面是有用的。

公开(公告)号：US20120309197A1

公开(公告)日：2012-12-06

申请号：US13151806

申请日：2011-06-02

Applicant: Hsing-Fei CHOU ,  Chia-Hua CHU ,  Jieh-Jang CHEN ,  Feng-Jia SHIU ,  Hung Chang HSIEH

Inventor： Hsing-Fei CHOU ,  Chia-Hua CHU ,  Jieh-Jang CHEN ,  Feng-Jia SHIU ,  Hung Chang HSIEH

IPC: H01L21/311

CPC classification number: B81C1/00063

Abstract: A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed.

Abstract translation: 形成半导体结构的方法包括在衬底中形成开口。 形成介电层并基本上与开口保持一致。 在开口内形成牺牲结构，覆盖电介质层的一部分。 通过使用牺牲结构作为蚀刻掩模层来去除介电层的一部分。 牺牲结构被去除。

公开(公告)号：US20120266810A1

公开(公告)日：2012-10-25

申请号：US13185009

申请日：2011-07-18

Applicant: Shun-Wei LAN ,  Jieh-Jang CHEN ,  Shih-Wei LIN ,  Feng-Jia SHIU ,  Hung Chang HSIEH

Inventor： Shun-Wei LAN ,  Jieh-Jang CHEN ,  Shih-Wei LIN ,  Feng-Jia SHIU ,  Hung Chang HSIEH

IPC: C23F1/08 ,  B05C11/00

CPC classification number: H01L21/31053 ,  H01L21/31058 ,  H01L21/31138

Abstract: A system for planarizing a semiconductor device includes a holder component for holding the substrate. The substrate has at least one opening therein, and each opening defines a lower portion and an upper portion. A resist applicator applies a layer of resist over the substrate, such that the resist layer covers the lower and upper portions. An etching component etches back the resist layer to expose the upper portion of the at least one opening. The resist applicator and the etching component repeat the steps of applying and etching, respectively, to remove a predetermined amount below the upper portion. A deposition component deposits an insulating layer over the substrate. A planarizing component planarizes the insulating layer until the upper portion of the at least one opening is exposed.

Abstract translation: 用于平坦化半导体器件的系统包括用于保持衬底的保持器部件。 衬底在其中具有至少一个开口，并且每个开口限定下部和上部。 抗蚀剂涂敷器在衬底上施加一层抗蚀剂，使得抗蚀剂层覆盖下部和上部。 蚀刻部件蚀刻抗蚀剂层以暴露至少一个开口的上部。 抗蚀剂涂布器和蚀刻部件分别重复施加和蚀刻的步骤，以去除上部下方的预定量。 沉积组分在衬底上沉积绝缘层。 平面化部件使绝缘层平坦化，直到暴露至少一个开口的上部。

公开(公告)号：US20060192083A1

公开(公告)日：2006-08-31

申请号：US10906604

申请日：2005-02-25

Applicant: Shih-Chi Fu ,  Yuan-Hung Liu ,  Kuo-Yin Lin ,  Feng-Jia Shiu ,  Chia-Shiung Tsai ,  Ching-Sen Kuo ,  Jieh-Jang Chen

Inventor： Shih-Chi Fu ,  Yuan-Hung Liu ,  Kuo-Yin Lin ,  Feng-Jia Shiu ,  Chia-Shiung Tsai ,  Ching-Sen Kuo ,  Jieh-Jang Chen

IPC: H01L27/00 ,  H01L31/00

CPC classification number: H01L27/14685 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/14654

Abstract: Described is a light-directing feature formed in the inter-level dielectric (ILD) layer in combination with an anti-reflective (AR) layer to effectively and simultaneously increase quantum efficiency and cross-talk immunity thereby improving photonic performances of photo-sensitive integrated circuits. A plurality of photosensor cells is formed on a semiconductor substrate. An AR layer is subsequently formed on the plurality of photosensor cells, the AR layer being substantially non-reflective of incident light. An ILD layer is then formed over the AR layer, the ILD layer comprising a plurality of light-directing features formed in openings in the ILD layer over the AR layer above and about certain of the plurality of photosensor cells.

Abstract translation: 描述了在层间电介质（ILD）层中形成的与抗反射（AR）层组合的光导特征，以有效并同时地提高量子效率和串扰抗扰度，从而改善光敏集成的光子性能 电路。 多个光电传感器单元形成在半导体基板上。 随后在多个光电传感器单元上​​形成AR层，AR层基本上不反射入射光。 然后在AR层上形成ILD层，ILD层包括多个导光特征，其形成在ILD层中的多个光敏元件上方和周围的AR层上的开口中。

公开(公告)号：US06803291B1

公开(公告)日：2004-10-12

申请号：US10394089

申请日：2003-03-20

Applicant: Shih-Chi Fu ,  Feng-Jia Shih ,  Chia-Tung Ho ,  Chih-Ta Wu ,  Ching-Sen Kuo ,  Jieh-Jang Chen ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsia

Inventor： Shih-Chi Fu ,  Feng-Jia Shih ,  Chia-Tung Ho ,  Chih-Ta Wu ,  Ching-Sen Kuo ,  Jieh-Jang Chen ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsia

IPC: H01L2176

CPC classification number: H01L21/76229 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for protecting an alignment mark area during a CMP process including forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.

Abstract translation: 一种用于在CMP工艺期间保护对准标记区域的方法，包括在半导体晶片的工艺表面上形成至少第一材料层，所述半导体晶片包括形成在所述至少一个对准标记区域中的有源区和对准标记沟槽; 在包括所述有源区域和所述至少一个对准标记区域的所述第一材料层上形成至少第二材料层; 对所述至少第二材料层进行光刻图案化和蚀刻，以形成与所述对准标记沟槽相邻的所述至少第二材料层的至少多条线; 以及执行CMP处理以去除所述至少第二材料层的至少一部分。

公开(公告)号：US08409456B2

公开(公告)日：2013-04-02

申请号：US13090763

申请日：2011-04-20

Applicant: Shun-Wei Lan ,  Jieh-Jang Chen ,  Shih-Wei Lin ,  Feng-Jia Shiu ,  Hung Chang Hsieh

Inventor： Shun-Wei Lan ,  Jieh-Jang Chen ,  Shih-Wei Lin ,  Feng-Jia Shiu ,  Hung Chang Hsieh

IPC: B44C1/22

CPC classification number: H01L21/31058 ,  H01L21/31138

Abstract: A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.

Abstract translation: 一种用于平面化半导体器件的方法包括提供其中具有至少一个开口的衬底，每个开口限定下部和上部; 在所述基板上涂覆感光材料层，所述光敏材料层覆盖所述至少一个开口的下部和上部; 蚀刻光敏材料层以暴露至少一个开口的上部; 重复涂覆和蚀刻步骤以除去至少一个开口的上部下方的预定量; 在衬底上沉积绝缘层; 并且平坦化绝缘层，直到暴露至少一个开口的上部。

公开(公告)号：US20120270398A1

公开(公告)日：2012-10-25

申请号：US13090763

申请日：2011-04-20

Applicant: Shun-Wei LAN ,  Jieh-Jang CHEN ,  Shih-Wei LIN ,  Feng-Jia SHIU ,  Hung Chang HSIEH

Inventor： Shun-Wei LAN ,  Jieh-Jang CHEN ,  Shih-Wei LIN ,  Feng-Jia SHIU ,  Hung Chang HSIEH

IPC: H01L21/3105 ,  H01L21/306

CPC classification number: H01L21/31058 ,  H01L21/31138

Abstract: A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.

Abstract translation: 一种用于平面化半导体器件的方法包括提供其中具有至少一个开口的衬底，每个开口限定下部和上部; 在所述基板上涂覆感光材料层，所述光敏材料层覆盖所述至少一个开口的下部和上部; 蚀刻光敏材料层以暴露至少一个开口的上部; 重复涂覆和蚀刻步骤以除去至少一个开口的上部下方的预定量; 在衬底上沉积绝缘层; 并且平坦化绝缘层，直到暴露至少一个开口的上部。

公开(公告)号：US20050274968A1

公开(公告)日：2005-12-15

申请号：US10982978

申请日：2004-11-05

Applicant: Ching-Sen Kuo ,  Feng-Jia Shiu ,  Gwo-Yuh Shiau ,  Jieh-Jang Chen ,  Shih-Chi Fu ,  Chien Tseng ,  Chia-Shiung Tsai ,  Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chih-Ta Wu ,  Chi-Hsin Lo

Inventor： Ching-Sen Kuo ,  Feng-Jia Shiu ,  Gwo-Yuh Shiau ,  Jieh-Jang Chen ,  Shih-Chi Fu ,  Chien Tseng ,  Chia-Shiung Tsai ,  Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chih-Ta Wu ,  Chi-Hsin Lo

IPC: H01L21/00 ,  H01L27/146 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/22 ,  H01L29/227 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L33/00 ,  H01L47/02

CPC classification number: H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687

Abstract: An image sensor includes a double-microlens structure with an outer microlens aligned over an inner microlens, both microlenses aligned over a corresponding photosensor. The inner or outer microlens may be formed by a silylation process in which a reactive portion of a photoresist material reacts with a silicon-containing agent. The inner or outer microlens may be formed by step etching of a dielectric material, the step etching process including a series of alternating etch steps including an anisotropic etching step and an etching step that causes patterned photoresist to laterally recede. Subsequent isotropic etching processes may be used to smooth the etched step structure and form a smooth lens. A thermally stable and photosensitive polymeric/organic material may also be used to form permanent inner or outer lenses. The photosensitive material is coated then patterned using photolithography, reflowed, then cured to form a permanent lens structure.

Abstract translation: 图像传感器包括双微透镜结构，其外部微透镜在内部微透镜上对准，两个微透镜在相应的光电传感器上对准。 内部或外部微透镜可以通过甲硅烷基化方法形成，其中光致抗蚀剂材料的反应性部分与含硅试剂反应。 内部或外部微透镜可以通过介电材料的步骤蚀刻形成，该步骤蚀刻工艺包括一系列交替蚀刻步骤，其包括各向异性蚀刻步骤和使图案化光致抗蚀剂横向后退的蚀刻步骤。 可以使用随后的各向同性蚀刻工艺来平滑蚀刻的台阶结构并形成光滑的透镜。 热稳定和感光的聚合物/有机材料也可用于形成永久的内镜片或外镜片。 感光材料被涂覆，然后使用光刻图案化，回流，然后固化以形成永久性透镜结构。

公开(公告)号：US08466070B2

公开(公告)日：2013-06-18

申请号：US13151806

申请日：2011-06-02

Applicant: Hsing-Fei Chou ,  Chia-Hua Chu ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Hung Chang Hsieh

Inventor： Hsing-Fei Chou ,  Chia-Hua Chu ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Hung Chang Hsieh

IPC: H01L21/311

CPC classification number: B81C1/00063

Abstract: A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed.

Abstract translation: 形成半导体结构的方法包括在衬底中形成开口。 形成介电层并基本上与开口保持一致。 在开口内形成牺牲结构，覆盖电介质层的一部分。 通过使用牺牲结构作为蚀刻掩模层来去除介电层的一部分。 牺牲结构被去除。