Invention Grant
- Patent Title: Planarization method for high wafer topography
- Patent Title (中): 高晶圆地形平面化方法
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Application No.: US13090763Application Date: 2011-04-20
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Publication No.: US08409456B2Publication Date: 2013-04-02
- Inventor: Shun-Wei Lan , Jieh-Jang Chen , Shih-Wei Lin , Feng-Jia Shiu , Hung Chang Hsieh
- Applicant: Shun-Wei Lan , Jieh-Jang Chen , Shih-Wei Lin , Feng-Jia Shiu , Hung Chang Hsieh
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman Ham & Berner, LLP
- Main IPC: B44C1/22
- IPC: B44C1/22

Abstract:
A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.
Public/Granted literature
- US20120270398A1 PLANARIZATION METHOD FOR HIGH WAFER TOPOGRAPHY Public/Granted day:2012-10-25
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