公开(公告)号：US08248864B2

公开(公告)日：2012-08-21

申请号：US12801859

申请日：2010-06-29

Applicant: Hidetoshi Ikeda ,  Koichi Takeda

Inventor： Hidetoshi Ikeda ,  Koichi Takeda

IPC: G11C5/06

CPC classification number: G11C7/1048 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/41 ,  G11C11/417 ,  G11C29/02 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254

Abstract: Provided is a semiconductor memory device including a plurality of memory cells that are connected to a word line and read data, a plurality of bit line pairs that are connected respectively to the plurality of memory cells, a column selector that selects one of the plurality of bit line pairs according to a column selection signal, a sense amplifier circuit that has an input terminal pair connected to the column selector and is activated according to a sense amplifier activation signal, an offset voltage adjustment circuit that is connected to the sense amplifier circuit and adjusts an offset voltage of the sense amplifier circuit according to the weight control signal, and a weight control circuit that is connected to an output terminal pair of the sense amplifier circuit and outputs a weight control signal with a value corresponding to an output of the activated sense amplifier circuit.

Abstract translation: 提供了一种半导体存储器件，包括连接到字线和读取数据的多个存储器单元，分别连接到多个存储器单元的多个位线对，选择多个存储单元中的一个的列选择器 根据列选择信号的位线对，具有连接到列选择器的输入端子对并根据读出放大器激活信号而被激活的读出放大器电路，连接到读出放大器电路的偏移电压调整电路和 根据加权控制信号调整读出放大器电路的偏移电压，以及加权控制电路，其连接到读出放大器电路的输出端子对，并输出加权控制信号，该加权控制信号具有对应于激活的输出的输出值 读出放大器电路。

公开(公告)号：US20110100861A1

公开(公告)日：2011-05-05

申请号：US12922615

申请日：2008-03-14

Applicant: Yuki Manabe ,  Tadaaki Inoue ,  Hideshi Okamoto ,  Keiichi Kawakawi ,  Koichi Takeda

Inventor： Yuki Manabe ,  Tadaaki Inoue ,  Hideshi Okamoto ,  Keiichi Kawakawi ,  Koichi Takeda

IPC: B65D85/00

CPC classification number: B65D1/095 ,  A61J1/067 ,  A61J2205/20 ,  Y10T428/1352

Abstract: An object of the present invention is to provide a plastic ampule capable of suppressing volatilization and scattering of a drug solution and elution of plastic compounding ingredients into the drug solution, as well as suppressing whisker formation and deformation and damage of an opening when the plastic ampule is opened. A plastic ampule 10 according to the present invention includes a drug solution storage part 11 for storing a drug solution, a drug solution discharge tube 12 in communication with the drug solution storage part 11 and extending toward one side, and a top part 13 closing an end at the one side of the drug solution discharge tube 12, and the drug solution discharge tube 12 includes a fragile part 14 formed to have a thin thickness along a circumferential direction. The drug solution storage part 11, the drug solution discharge tube 12, and the top part 13 are formed of a multilayer plastic material that includes an intermediate layer containing a cyclic olefin-based (co)polymer with a glass transition temperature of 60 to 80° C., an inner layer laminated to an inner side of the intermediate layer, an outer layer laminated to an outer side of the intermediate layer, and adhesive layers respectively disposed between the intermediate layer and the inner layer and between the outer layer and the intermediate layer.

Abstract translation: 本发明的目的是提供一种塑料安瓿，其能够抑制药液的挥发和飞散，并且将塑料配料成分溶解到药液中，并且当塑料安瓿处理时抑制晶须的形成和变形以及开口的损坏 开了 根据本发明的塑料安瓿10包括用于储存药液的药液存储部分11，与药液存储部分11连通并向一侧延伸的药液放电管12， 在药液排出管12的一侧端部，药液排出管12包括沿圆周方向形成为具有薄的厚度的脆性部14。 药液存储部11，药液排出管12以及顶部13由多层塑料材料形成，该多层塑料材料包含中间层，该中间层含有玻璃化转变温度为60〜80℃的环状烯烃系（共）聚合物 ℃，层压到中间层的内侧的内层，层压到中间层的外侧的外层，以及分别设置在中间层和内层之间以及外层和内层之间的粘合层 中间层。

公开(公告)号：US20100289091A1

公开(公告)日：2010-11-18

申请号：US12095663

申请日：2006-12-01

Applicant: Koichi Takeda ,  Kiyoshi Takeuchi

Inventor： Koichi Takeda ,  Kiyoshi Takeuchi

IPC: H01L27/088 ,  H01L21/8239

CPC classification number: H01L21/845 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  Y10S257/903

Abstract: A semiconductor device is provided with an SRAM cell unit. The SRAM cell unit is provided with a data storing section composed of a pair of drive transistors and a pair of load transistors; a data write section composed of a pair of access transistors; and a data read section composed of an access transistor and a drive transistor. Each of the transistors is provided with a semiconductor layer protruding from a base plane; a gate electrode extending on the both facing side planes over the semiconductor layer from above; a gate insulating film between a gate electrode and a semiconductor layer; and a source/drain region. Each semiconductor layer is arranged to have its longitudinal direction along a first direction. In the adjacent SRAM cell units in the first direction, all the corresponding transistors have the semiconductor layer of one transistor on a center line which is along the first direction of the semiconductor layer of the other transistor.

Abstract translation: 半导体器件设置有SRAM单元单元。 SRAM单元单元设置有由一对驱动晶体管和一对负载晶体管组成的数据存储部; 由一对存取晶体管组成的数据写入部分; 以及由存取晶体管和驱动晶体管构成的数据读取部。 每个晶体管设置有从基底面突出的半导体层; 从上方在半导体层上方的两面相对的侧面上延伸的栅电极; 在栅电极和半导体层之间的栅极绝缘膜; 和源极/漏极区域。 每个半导体层被布置成沿着第一方向具有其纵向方向。 在第一方向的相邻SRAM单元单元中，所有对应的晶体管都具有沿着另一个晶体管的半导体层的第一方向的中心线上的一个晶体管的半导体层。

公开(公告)号：US07826253B2

公开(公告)日：2010-11-02

申请号：US11815415

申请日：2006-02-03

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C11/00

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/092

Abstract: In a reading operation, an off time and a reading time of a holding control transistor is controlled by a replica circuit, so that a read margin is enlarged. Furthermore, a high power source potential and a low power source potential of an SRAM memory cell are switched in reading and writing operations of the memory cell and in a data holding state by a power source potential switching portion. As a result, a write margin is enlarged, and a leakage current is reduced.

Abstract translation: 在读取操作中，由复制电路控制保持控制晶体管的关闭时间和读取时间，从而放大读取余量。 此外，SRAM存储单元的高电源电位和低电源电位在存储单元的读取和写入操作中被切换，并且在电源电位切换部分处于数据保持状态。 结果，写入裕度被放大，并且漏电流减小。

公开(公告)号：US20100141301A1

公开(公告)日：2010-06-10

申请号：US12518793

申请日：2007-12-12

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C8/10 ,  H03K19/0948

CPC classification number: H03K19/0016 ,  G11C7/22 ,  G11C7/225 ,  G11C8/10 ,  G11C8/18 ,  G11C2207/2227 ,  H03K19/20

Abstract: Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.

Abstract translation: 公开了一种逻辑电路，包括接收第一脉冲信号和第一选择信号的第一NAND门，反相第一NAND门的输出信号以输出结果信号的第一反相器门，接收第二NAND门的第二NAND门 脉冲信号和第一选择信号;第二反相器门，反相第二与非门的输出信号;第一PMOS晶体管，漏极端连接到第一与非门的输出;栅极， 第二NAND门和连接到电源电压的源极端子，以及第一NMOS晶体管，漏极端子连接到第一反相器栅极的输出，栅极端子连接到第二反相器栅极的输出端，源极端子连接 到地下潜力。

公开(公告)号：US07659772B2

公开(公告)日：2010-02-09

申请号：US11813502

申请日：2006-01-06

Applicant: Masahiro Nomura ,  Koichi Takeda

Inventor： Masahiro Nomura ,  Koichi Takeda

IPC: G05F1/10

CPC classification number: H03K19/0008

Abstract: A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.

Abstract translation: 一种半导体集成电路器件，包括：用于观察开关电流的开关电流观察器; 用于观察泄漏电流的漏电流观测器; 将开关电流和漏电流进行比较的比较器; 用于控制衬底偏置电压以使开关电流和漏电流的比率恒定的阈值电压控制器; 用于观察延迟量的延迟观察器; 以及用于控制电源电压以便将延迟量保持在预定范围内的电源电压控制器。 在半导体集成电路器件中，通过控制阈值电压来实现能够最小化操作功率的处理，以使给定时钟频率下的开关电流和漏电流的比率恒定，并将电源电压控制为 保证运行速度。

公开(公告)号：US20090069445A1

公开(公告)日：2009-03-12

申请号：US11910419

申请日：2006-04-07

Applicant: Koichi Takeda ,  Kenji Matsuda ,  Toshimitsu Terao ,  Tadaaki Inoue ,  Takashi Imagawa ,  Shigeru Masumi

Inventor： Koichi Takeda ,  Kenji Matsuda ,  Toshimitsu Terao ,  Tadaaki Inoue ,  Takashi Imagawa ,  Shigeru Masumi

IPC: A61K31/05 ,  A61P25/00

CPC classification number: A61K9/1075 ,  A61K9/0019 ,  A61K9/107 ,  A61K31/05

Abstract: This invention provides a propofol-containing fat emulsion preparation including: 0.1 to 2 w/v % of propofol, 10 to 20 w/v % of an oily component, and 2 to 5 w/v % of an emulsifier, the weight of the oily component being in the range of about 5 to about 200 times the weight of propofol, the weight of the emulsifier being in the range of about 0.9 to about 50 times that of propofol, and the average size of emulsion particles being 180 nm or less, and a method for preparing the same. Propofol-containing fat emulsion preparation of this invention alleviates the vascular pain that occurs during the administration thereof without incorporating a local anesthetic, such as lidocaine or the like, therein.

Abstract translation: 本发明提供含异丙酚的脂肪乳液制剂，其包含：0.1〜2w / v％的异丙酚，10〜20w / v％的油性成分和2〜5w / v％的乳化剂， 油性成分在丙泊酚重量的约5至约200倍的范围内，乳化剂的重量在丙泊酚的约0.9至约50倍的范围内，乳液颗粒的平均尺寸为180nm或更小 ，及其制备方法。 本发明的含异丙酚的脂肪乳液制剂减轻了在施用期间发生的血管疼痛，而没有在其中掺入局部麻醉剂，例如利多卡因等。

公开(公告)号：US20090014795A1

公开(公告)日：2009-01-15

申请号：US11658564

申请日：2005-07-14

Applicant: Risho Koh ,  Katsuhiko Tanaka ,  Shigeharu Yamagami ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda

Inventor： Risho Koh ,  Katsuhiko Tanaka ,  Shigeharu Yamagami ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A π gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.

Abstract translation: 提供了一种具有减小的截止电流和寄生电容的变化的p型门FinFET结构及其制造方法。 改善了元件的结构，使得能够更强烈地显示出截止电流的能力。 一种场效应晶体管，其中第一绝缘膜和半导体区域设置成相对于基底的平坦表面向上突出，所述场效应晶体管具有栅极电极，栅极绝缘膜和源极/漏极区域 并且至少在所述半导体区域的侧表面上形成沟道，其中所述第一绝缘膜设置在由蚀刻速率低于所述第一绝缘膜的最下层的蚀刻速率的材料构成的蚀刻停止层上 用于在预定条件下蚀刻。

公开(公告)号：US07319696B2

公开(公告)日：2008-01-15

申请号：US10162793

申请日：2002-06-05

Applicant: Rumiko Inoue ,  Satoshi Tsuchiya ,  Koichi Takeda

Inventor： Rumiko Inoue ,  Satoshi Tsuchiya ,  Koichi Takeda

IPC: H04L12/56

CPC classification number: H04L29/06 ,  H04L47/2408 ,  H04L67/327 ,  H04L69/22 ,  H04L69/329

Abstract: In a communication system, a first communication apparatus includes: an application data generating unit for generating application data including data at an application level and a priority at the application level; and a lower-level packet generating unit disposed therein for generating a packet by adding to the application data a header including a destination address and a source address at a level lower than the application level. A first relay apparatus includes: a priority identifying unit disposed therein for determining whether or not a priority is set in the application data of the packet received by the first relay apparatus, and thereby identifying a first priority at the application level; and a priority control unit disposed therein for renewing a TOS field value in the header of the packet, the header being at the level lower than the application level, on the basis of the first priority.

Abstract translation: 在通信系统中，第一通信装置包括：应用数据生成单元，用于生成包括应用级的数据和应用层的优先级的应用数据; 以及其中设置的低级分组产生单元，用于通过向应用数据添加包括目的地地址和低于应用级别的源地址的报头来生成分组。 第一中继装置包括：优先级识别单元，其设置在其中，用于确定在第一中继装置接收到的分组的应用数据中是否设置了优先级，从而在应用级别识别第一优先级; 以及设置在其中的优先级控制单元，用于基于所述第一优先级更新所述分组的报头中的TOS字段值，所述报头位于比所述应用级别低的水平。

公开(公告)号：US20070187682A1

公开(公告)日：2007-08-16

申请号：US10569451

申请日：2004-08-27

Applicant: Kiyoshi Takeuchi ,  Koji Watanabe ,  Koichi Terashima ,  Atsushi Ogura ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka ,  Shigeharu Yamagami ,  Hitoshi Wakabayashi

Inventor： Kiyoshi Takeuchi ,  Koji Watanabe ,  Koichi Terashima ,  Atsushi Ogura ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka ,  Shigeharu Yamagami ,  Hitoshi Wakabayashi

IPC: H01L29/04

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7854

Abstract: There is provided a semiconductor device comprising an n-type and a p-type field effect transistors, meeting the conditions that in terms of a crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {100} plane substantially orthogonal to the {100} plane, and that in terms of a crystal orientation of the protruding semiconductor region constituting the p-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {110} plane substantially orthogonal to the {100} plane.

Abstract translation: 提供一种包括n型和p型场效应晶体管的半导体器件，满足以下条件：就组成n型场效应晶体管的突出半导体区域的晶体取向而言，其平行于衬底的平面 基本上是{100}面，其侧面是与{100}面大致正交的{100}面，就构成p型场效应晶体管的突出半导体区域的晶体取向而言，其平面 与基板平行的基本上是{100}平面，其侧面是与{100}平面基本正交的{110}平面。