公开(公告)号：US20130196485A1

公开(公告)日：2013-08-01

申请号：US13362398

申请日：2012-01-31

Applicant: Nicholas LiCausi ,  Jeremy Wahl

Inventor： Nicholas LiCausi ,  Jeremy Wahl

IPC: H01L21/20

CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: Disclosed herein are various methods for better height control of the finFET patterned fins. In one example, this invention begins by depositing or growing an oxide material, for example, silicon dioxide. This oxide material is then patterned and etched to open windows or trenches to the substrate where fins will be grown. If a common channel material is desired, it is epitaxially grown in the windows. Then, some windows are covered and one pole of fins (for example nFET) are epitaxially grown in the exposed windows. The previously masked windows are opened and the newly formed fins are masked. The alternate channel material is then grown. The masked fins are then un-masked and the oxide is recessed to allow the fins to protrude from the oxide. This invention also allows for different channel materials for NMOS and PMOS.

Abstract translation: 这里公开了用于更好地控制finFET图案的翅片的各种方法。 在一个实例中，本发明通过沉积或生长氧化物材料，例如二氧化硅开始。 然后对该氧化物材料进行图案化和蚀刻以将窗口或沟槽打开到衬底，其中翅片将被生长。 如果需要共同的通道材料，则在窗户中外延生长。 然后，覆盖一些窗口，并且在暴露的窗口中外延生长鳍的一个极（例如nFET）。 先前掩蔽的窗户被打开，并且新形成的翅片被掩蔽。 然后生长替代通道材料。 掩蔽的翅片然后被掩蔽，并且氧化物凹陷以允许翅片从氧化物突出。 本发明还允许用于NMOS和PMOS的不同通道材料。

公开(公告)号：US20120313169A1

公开(公告)日：2012-12-13

申请号：US13156578

申请日：2011-06-09

Applicant: Jeremy Wahl ,  Kingsuk Maitra

Inventor： Jeremy Wahl ,  Kingsuk Maitra

IPC: H01L27/12 ,  H01L21/66 ,  H01L21/84

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L22/12 ,  H01L22/20

Abstract: FIN-FET ICs with adjustable FIN-FET channel widths are formed from a semiconductor layer (42). Fins (36) may be etched from the layer (42) and then some (46) locally shortened or the layer (42) may be locally thinned and then fins (46) of different fin heights etched therefrom. Either way provides fins (46) and FIN-FETs (40) with different channel widths W on the same substrate (24). Fin heights (H) are preferably shortened by implanting selected ions (A, B, C, etc.) through a mask (90, 90′, 94, 94′, 97, 97′) to locally enhance the etch rate of the layer (42) or some of the fins (36). The implant(s) (A, B, C, etc.) is desirably annealed and then differentially etched. This thins part(s) (42-i) of the layer (42) from which the fins (46) are then etched or shortens some of the fins (46) already etched from the layer (42). For silicon, germanium is a suitable implant ion. Having fins (42) with adjustable fin heights Hi on the same substrate (24) enables such FIN-FET ICs (40) to avoid channel-width quantization effects observed with prior art uniform fin height FIN-FETs (20).

Abstract translation: 具有可调节FIN-FET沟道宽度的FIN-FET IC由半导体层（42）形成。 金属丝（36）可以从层（42）蚀刻，然后一些（46）局部缩短或层（42）可以局部变薄，然后从其中蚀刻不同翅片高度的翅片（46）。 无论哪种方式都在同一衬底（24）上提供具有不同通道宽度W的翅片（46）和FIN-FET（40）。 翅片高度（H）优选通过将选择的离子（A，B，C等）通过掩模（90,90'，94,94'，97,97'）注入来局部地提高层的蚀刻速率来缩短 （42）或一些翅片（36）。 植入物（A，B，C等）理想地退火然后进行差异蚀刻。 这样使得层（42）的部分（42-i）沉淀，然后从其中蚀刻或缩短已经从层（42）蚀刻的一些翅片（46）。 对于硅，锗是合适的注入离子。 在同一衬底（24）上具有可调翅片高度Hi的翅片（42）使得这种FIN-FET IC（40）避免了现有技术的均匀翅片高度FIN-FET（20）观察到的通道宽度量化效应。

公开(公告)号：US08476137B1

公开(公告)日：2013-07-02

申请号：US13370722

申请日：2012-02-10

Applicant: Nicholas LiCausi ,  Jeremy Wahl

Inventor： Nicholas LiCausi ,  Jeremy Wahl

IPC: H01L21/336

CPC classification number: H01L21/823431 ,  H01L21/845

Abstract: Disclosed herein are methods for better variable height control of FinFET patterned fins. In one example, the method includes forming a layer on a substrate, patterning that layer to create trenches, and forming a common stack material in the trenches. Next, a pFET masking material is formed over a portion of the structure, and an nFET channel material is formed in the unmasked trenches. The pFET masking material is removed and an nFET masking material is formed over the portion of the structure that includes the nFET channel material, and a pFET channel material is formed in the unmasked trenches. Next, the unmasked patterned material is made flush with the pFET channel material, thereby creating a difference in height with the masked pattern material. Finally, the nFET masking material is removed and the patterned layer is recessed to expose pFET and nFET channel material fin structures of differing heights.

Abstract translation: 这里公开了用于FinFET图案化翅片的更好的可变高度控制的方法。 在一个实例中，该方法包括在衬底上形成层，图案化该层以产生沟槽，以及在沟槽中形成共同的堆叠材料。 接下来，在结构的一部分上形成pFET掩模材料，并且在未掩模的沟槽中形成nFET沟道材料。 除去pFET掩模材料，并且在包括nFET沟道材料的结构的部分上形成nFET掩模材料，并且在未掩模的沟槽中形成pFET沟道材料。 接下来，未屏蔽的图案化材料与pFET沟道材料齐平，从而与掩模图案材料形成高度差异。 最后，去除nFET掩模材料，并且图案化层被凹入以暴露不同高度的pFET和nFET沟道材料鳍结构。

公开(公告)号：US07998846B2

公开(公告)日：2011-08-16

申请号：US12209478

申请日：2008-09-12

Applicant: Eunha Kim ,  Jeremy Wahl ,  Shenqing Fang ,  YouSeok Suh ,  Kuo-Tung Chang ,  Yi Ma ,  Rinji Sugino ,  Jean Yang

Inventor： Eunha Kim ,  Jeremy Wahl ,  Shenqing Fang ,  YouSeok Suh ,  Kuo-Tung Chang ,  Yi Ma ,  Rinji Sugino ,  Jean Yang

IPC: H01L21/263

CPC classification number: H01L21/02675 ,  H01L21/02592 ,  H01L21/02691

Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

Abstract translation: 提出了半导体制造系统和方法。 三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。 可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。

公开(公告)号：US08460984B2

公开(公告)日：2013-06-11

申请号：US13156578

申请日：2011-06-09

Applicant: Jeremy Wahl ,  Kingsuk Maitra

Inventor： Jeremy Wahl ,  Kingsuk Maitra

IPC: H01L21/84

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L22/12 ,  H01L22/20

Abstract: FIN-FET ICs with adjustable FIN-FET channel widths are formed from a semiconductor layer (42). Fins (36) may be etched from the layer (42) and then some (46) locally shortened or the layer (42) may be locally thinned and then fins (46) of different fin heights etched therefrom. Either way provides fins (46) and FIN-FETs (40) with different channel widths W on the same substrate (24). Fin heights (H) are preferably shortened by implanting selected ions (A, B, C, etc.) through a mask (90, 90′, 94, 94′, 97, 97′) to locally enhance the etch rate of the layer (42) or some of the fins (36). The implant(s) (A, B, C, etc.) is desirably annealed and then differentially etched. This thins part(s) (42-i) of the layer (42) from which the fins (46) are then etched or shortens some of the fins (46) already etched from the layer (42). For silicon, germanium is a suitable implant ion. Having fins (42) with adjustable fin heights Hi on the same substrate (24) enables such FIN-FET ICs (40) to avoid channel-width quantization effects observed with prior art uniform fin height FIN-FETs (20).

Abstract translation: 具有可调节FIN-FET沟道宽度的FIN-FET IC由半导体层（42）形成。 金属丝（36）可以从层（42）蚀刻，然后一些（46）局部缩短或层（42）可以局部变薄，然后从其中蚀刻不同翅片高度的翅片（46）。 无论哪种方式都在同一衬底（24）上提供具有不同通道宽度W的翅片（46）和FIN-FET（40）。 翅片高度（H）优选通过将选择的离子（A，B，C等）通过掩模（90,90'，94,94'，97,97'）注入来局部地提高层的蚀刻速率来缩短 （42）或一些翅片（36）。 植入物（A，B，C等）理想地退火然后进行差异蚀刻。 这样使得层（42）的部分（42-i）沉淀，然后从其中蚀刻或缩短已经从层（42）蚀刻的一些翅片（46）。 对于硅，锗是合适的注入离子。 在同一衬底（24）上具有可调翅片高度Hi的翅片（42）使得这种FIN-FET IC（40）避免了现有技术的均匀翅片高度FIN-FET（20）观察到的通道宽度量化效应。

公开(公告)号：US08481410B1

公开(公告)日：2013-07-09

申请号：US13362398

申请日：2012-01-31

Applicant: Nicholas LiCausi ,  Jeremy Wahl

Inventor： Nicholas LiCausi ,  Jeremy Wahl

IPC: H01L21/20

CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: Disclosed herein are various methods for better height control of the finFET patterned fins. In one example, this invention begins by depositing or growing an oxide material, for example, silicon dioxide. This oxide material is then patterned and etched to open windows or trenches to the substrate where fins will be grown. If a common channel material is desired, it is epitaxially grown in the windows. Then, some windows are covered and one pole of fins (for example nFET) are epitaxially grown in the exposed windows. The previously masked windows are opened and the newly formed fins are masked. The alternate channel material is then grown. The masked fins are then un-masked and the oxide is recessed to allow the fins to protrude from the oxide. This invention also allows for different channel materials for NMOS and PMOS.

Abstract translation: 这里公开了用于更好地控制finFET图案的翅片的各种方法。 在一个实例中，本发明通过沉积或生长氧化物材料，例如二氧化硅开始。 然后对该氧化物材料进行图案化和蚀刻以将窗口或沟槽打开到衬底，其中翅片将被生长。 如果需要共同的通道材料，则在窗户中外延生长。 然后，覆盖一些窗口，并且在暴露的窗口中外延生长鳍的一个极（例如nFET）。 先前掩蔽的窗户被打开，并且新形成的翅片被掩蔽。 然后生长替代通道材料。 掩蔽的翅片然后被掩蔽，并且氧化物凹陷以允许翅片从氧化物突出。 本发明还允许用于NMOS和PMOS的不同通道材料。

公开(公告)号：US20110272775A1

公开(公告)日：2011-11-10

申请号：US13183373

申请日：2011-07-14

Applicant: Eunha KIM ,  Jeremy WAHL ,  Shenqing FANG ,  YouSeok SUH ,  Kuo-Tung CHANG ,  Yi MA ,  Rinji SUGINO ,  Jean YANG

Inventor： Eunha KIM ,  Jeremy WAHL ,  Shenqing FANG ,  YouSeok SUH ,  Kuo-Tung CHANG ,  Yi MA ,  Rinji SUGINO ,  Jean YANG

IPC: H01L29/02

CPC classification number: H01L21/02675 ,  H01L21/02592 ,  H01L21/02691

Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

Abstract translation: 提出了半导体制造系统和方法。 三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。 可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。

公开(公告)号：US20100065940A1

公开(公告)日：2010-03-18

申请号：US12209478

申请日：2008-09-12

Applicant: Eunha KIM ,  Jeremy WAHL ,  Shenqing FANG ,  YouSeok SUH ,  Kuo-Tung CHANG ,  Yi MA ,  Rinji SUGINO ,  Jean YANG

Inventor： Eunha KIM ,  Jeremy WAHL ,  Shenqing FANG ,  YouSeok SUH ,  Kuo-Tung CHANG ,  Yi MA ,  Rinji SUGINO ,  Jean YANG

IPC: H01L29/00 ,  H01L21/00

CPC classification number: H01L21/02675 ,  H01L21/02592 ,  H01L21/02691

Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

Abstract translation: 提出了半导体制造系统和方法。 三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。 可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。