公开(公告)号：US07924102B2

公开(公告)日：2011-04-12

申请号：US12390648

申请日：2009-02-23

Applicant: Jeffrey M. Hinrichs

Inventor： Jeffrey M. Hinrichs

IPC: H03K3/03

CPC classification number: H03K3/0322 ,  H03F3/45659 ,  H03F2203/45636 ,  H03F2203/45668 ,  H03F2203/45671

Abstract: An oscillator includes a control circuit and a ring of symmetric load delay cells. Each delay cell includes two novel symmetric loads. Each load involves a level shift circuit and a diode-connected transistor coupled in parallel with a current source-connected transistor. The control circuit converts an oscillator input signal into bias control signals that in turn control the effective resistance of the symmetric loads such that delays through the delay cells are a function of the input signal. The control circuit uses a symmetric load replica in a control loop to control the level shift circuits of the delay cells such that the oscillating delay cell output signals have a constant amplitude. In a first advantageous aspect, due to the constant amplitude, the oscillator is operable over a wide frequency range. In a second advantageous aspect, the oscillator input signal to output signal oscillation frequency has a substantially linear relationship.

Abstract translation: 振荡器包括控制电路和对称负载延迟单元的环。 每个延迟单元包括两个新的对称负载。 每个负载涉及与电流源连接的晶体管并联耦合的电平移位电路和二极管连接的晶体管。 控制电路将振荡器输入信号转换成偏置控制信号，该偏置控制信号又控制对称负载的有效电阻，使得通过延迟单元的延迟是输入信号的函数。 控制电路使用控制回路中的对称负载复制来控制延迟单元的电平移位电路，使得振荡延迟单元输出信号具有恒定的幅度。 在第一有利的方面，由于恒定幅度，振荡器可在宽的频率范围内操作。 在第二有利的方面，振荡器输入信号到输出信号振荡频率具有基本上的线性关系。

公开(公告)号：US06897799B1

公开(公告)日：2005-05-24

申请号：US10897240

申请日：2004-07-22

Applicant: Harry S. Harberts ,  Jeffrey M. Hinrichs

Inventor： Harry S. Harberts ,  Jeffrey M. Hinrichs

IPC: H03K17/041 ,  H03K17/16 ,  H03M1/06 ,  H03M1/74 ,  H03M3/00 ,  H03M3/02 ,  H03M1/66

CPC classification number: H03M1/06 ,  H03K17/04113 ,  H03K17/16 ,  H03M1/742 ,  H03M3/348 ,  H03M3/502

Abstract: A digital-to-analog converter having a differential signal path, and a current parking circuit that is independent of the signal path, thereby avoiding a source of imbalance that caused output anomalies in conventional digital-to-analog circuitry. In one embodiment of the invention, a pair of diodes in the current parking circuit are connected through their own independent load resistors to a voltage source. In another embodiment, a single diode is used instead of the pair of diodes, and in a third embodiment the current parking circuit comprises a single load resistor connected to the voltage source, and no diodes at all.

Abstract translation: 具有差分信号路径的数模转换器和独立于信号路径的当前停车电路，从而避免在常规数模转换电路中引起输出异常的不平衡源。 在本发明的一个实施例中，当前停车电路中的一对二极管通过它们自己的独立负载电阻器连接到电压源。 在另一个实施例中，使用单个二极管代替一对二极管，并且在第三实施例中，当前的停车电路包括连接到电压源的单个负载电阻器，并且根本不存在二极管。

公开(公告)号：US20100214032A1

公开(公告)日：2010-08-26

申请号：US12390648

申请日：2009-02-23

Applicant: Jeffrey M. Hinrichs

Inventor： Jeffrey M. Hinrichs

IPC: H03K3/021

CPC classification number: H03K3/0322 ,  H03F3/45659 ,  H03F2203/45636 ,  H03F2203/45668 ,  H03F2203/45671

Abstract: An oscillator includes a control circuit and a ring of symmetric load delay cells. Each delay cell includes two novel symmetric loads. Each load involves a level shift circuit and a diode-connected transistor coupled in parallel with a current source-connected transistor. The control circuit converts an oscillator input signal into bias control signals that in turn control the effective resistance of the symmetric loads such that delays through the delay cells are a function of the input signal. The control circuit uses a symmetric load replica in a control loop to control the level shift circuits of the delay cells such that the oscillating delay cell output signals have a constant amplitude. In a first advantageous aspect, due to the constant amplitude, the oscillator is operable over a wide frequency range. In a second advantageous aspect, the oscillator input signal to output signal oscillation frequency has a substantially linear relationship.

Abstract translation: 振荡器包括控制电路和对称负载延迟单元的环。 每个延迟单元包括两个新的对称负载。 每个负载涉及与电流源连接的晶体管并联耦合的电平移位电路和二极管连接的晶体管。 控制电路将振荡器输入信号转换成偏置控制信号，该偏置控制信号又控制对称负载的有效电阻，使得通过延迟单元的延迟是输入信号的函数。 控制电路使用控制回路中的对称负载复制来控制延迟单元的电平移位电路，使得振荡延迟单元输出信号具有恒定的幅度。 在第一有利的方面，由于恒定幅度，振荡器可在宽的频率范围内操作。 在第二有利的方面，振荡器输入信号到输出信号振荡频率具有基本上的线性关系。

公开(公告)号：US20090103750A1

公开(公告)日：2009-04-23

申请号：US12237786

申请日：2008-09-25

Applicant: Uma Chilakapati ,  Seyfollah Bazarjani ,  Joseph Fitzgerald ,  Guoqing Miao ,  Hui-Ya Nelson ,  Khalid J. Sidiqi ,  Jeffrey M. Hinrichs

Inventor： Uma Chilakapati ,  Seyfollah Bazarjani ,  Joseph Fitzgerald ,  Guoqing Miao ,  Hui-Ya Nelson ,  Khalid J. Sidiqi ,  Jeffrey M. Hinrichs

IPC: H04B15/00

CPC classification number: H03M3/384 ,  H03M1/1019 ,  H03M1/66 ,  H03M3/50

Abstract: A digital offset is combined with an audio signal in the digital domain to cancel an output offset caused by one or more analog components processing the same audio signal. In this manner, the offset at the output of the audio signal path (e.g., at a power amplifier output) is reduced or eliminated. Consequently, audible artifacts, such as click-and-pop artifacts, can be reduced or eliminated. In audio devices operating in ground-referenced capless mode, power consumption is reduced because of reduced or eliminated direct current (DC) leakage current through speakers or headsets of such audio devices. In some circumstances, the digital offset in the digital domain may be applied at substantially all times of operation of the audio signal path.

Abstract translation: 数字偏移与数字域中的音频信号组合以消除由处理相同音频信号的一个或多个模拟分量引起的输出偏移。 以这种方式，减少或消除音频信号路径输出处的偏移（例如，在功率放大器输出端）。 因此，可以减少或消除诸如点击和流行伪像的声音伪影。 在以地面参考无盖模式工作的音频设备中，由于减少或消除了通过这种音频设备的扬声器或耳机的直流（DC）泄漏电流，功耗被降低。 在某些情况下，数字域中的数字偏移可以在音频信号路径的操作的基本上全部被应用。

公开(公告)号：US07301392B2

公开(公告)日：2007-11-27

申请号：US11203579

申请日：2005-08-10

Applicant: Jeffrey M. Hinrichs ,  William R. Goyette

Inventor： Jeffrey M. Hinrichs ,  William R. Goyette

IPC: H03K5/00

CPC classification number: H03H11/1291 ,  H03H11/1252

Abstract: An integrated circuit (IC) resonator in which resonator parameters potentially affected by IC fabrication processes are correctable after fabrication. Resonance frequency tuning is effected by forming each feedback capacitor in a pair of integrator circuits to include a variable capacitance device, such as a varactor diode. A tuning signal is applied to the varactor diode to adjust the total capacitance value and, therefore, the resonance frequency. Similarly, the quality (Q) factor of the resonator is adjusted by providing a variable capacitance in an RC (resistance-capacitance) network coupling the output of one of the integrator circuits to the input of the other. The variable capacitance in the RC network permits adjustment of phase in the event that the integrator circuits do not provide a desired 180° total phase shift.

公开(公告)号：US07183956B1

公开(公告)日：2007-02-27

申请号：US11202307

申请日：2005-08-10

Applicant: Jeffrey M. Hinrichs ,  Harry S. Harberts

Inventor： Jeffrey M. Hinrichs ,  Harry S. Harberts

IPC: H03M3/02

CPC classification number: H03H17/0657 ,  H03M3/508 ,  H03M7/3017 ,  H03M7/3035 ,  H03M7/304

Abstract: Apparatus, and a related method, for converting digital signals directly to radio-frequency (RF) analog signals. The apparatus includes a single high-speed delta-sigma modulator and an integrated upsampler that increases the data rate of digital input samples by a selected factor, such as nine times. The delta-sigma modulator is configured to include a feedback multiplier coefficients that are selected to greatly facilitate operation of associated adders. At least one critical adder includes a carry-select adder modification that further speeds up the add operation and ensures that the apparatus operates at desirably high frequencies.

Abstract translation: 用于将数字信号直接转换成射频（RF）模拟信号的装置和相关方法。 该装置包括单个高速Δ-Σ调制器和集成上采样器，其通过选择的因子（例如九次）来增加数字输入样本的数据速率。 Δ-Σ调制器被配置为包括被选择以极大地促进相关加法器的操作的反馈乘法器系数。 至少一个关键加法器包括进位选择加法器修改，进一步加速加法运算，并确保装置以期望的高频工作。

公开(公告)号：US07031395B2

公开(公告)日：2006-04-18

申请号：US10109834

申请日：2002-03-29

Applicant: Jeffrey M. Hinrichs ,  Brian J. Rosenkoetter ,  Robert R. Harnden ,  Kenneth B. Weber ,  Mark Kintis ,  Donald R. Martin ,  William M. Skones ,  Kai E. Johnson

Inventor： Jeffrey M. Hinrichs ,  Brian J. Rosenkoetter ,  Robert R. Harnden ,  Kenneth B. Weber ,  Mark Kintis ,  Donald R. Martin ,  William M. Skones ,  Kai E. Johnson

IPC: H03M3/00 ,  H04B14/06

CPC classification number: H03M7/302 ,  H03M3/50 ,  H04L5/023 ,  H04L27/2627

Abstract: An apparatus for converting a digital input signal to an analog signal for transmission. The input signal can include more than one carrier signal. A plurality of delta-sigma modulation loop circuits are connected in an increasing order of operating frequency so as to reduce a word length of the input signal. A tuning circuit adjusts the signal frequency to a transmitting frequency for conversion to analog by a digital-to-analog converter. A first loop circuit is implemented using CMOS gates, and a second loop circuit and the tuning circuit are implemented using indium phosphide gates. The apparatus allows a high-resolution, wide-band RF multiple-carrier signal to be re-quantized to a lower-resolution signal while an acceptable signal-to-noise ratio is maintained.