公开(公告)号：US09509259B2

公开(公告)日：2016-11-29

申请号：US14969063

申请日：2015-12-15

申请人： FUJITSU LIMITED

发明人： Hideki Oku

IPC分类号： H03F3/04 ,  H03F3/08 ,  H03F3/50 ,  H03F3/45

CPC分类号： H03F3/08 ,  H03F3/45103 ,  H03F3/50 ,  H03F2203/45601 ,  H03F2203/45612 ,  H03F2203/45668

摘要： An amplifier 12 including a first transistor 23 which is a common base transistor and whose emitter current fluctuates in accordance with fluctuations in an input current that is input to the emitter, a second transistor 24 which is a common base transistor, whose emitter is connected to the collector of the first transistor 23, and whose collector voltage fluctuates in accordance with fluctuations in the emitter current of the first transistor 23, a third transistor 31 which is a common collector transistor and whose base is connected to the collector of the second transistor 24, and an amplification unit 40 to which an emitter voltage of the third transistor 3 is input and which outputs an amplified voltage obtained by amplifying the emitter voltage of the third transistor, wherein the base resistance of the second transistor 24 is higher than the base resistance of the first transistor 23.

摘要翻译： 放大器12，其包括作为公共基极晶体管的第一晶体管23，其发射极电流根据输入到发射极的输入电流的波动而波动;第二晶体管24，其是发射极连接到 第一晶体管23的集电极，其集电极电压根据第一晶体管23的发射极电流的波动而波动;第三晶体管31，其是公共集电极晶体管，其基极连接到第二晶体管24的集电极 以及放大单元40，输入第三晶体管3的发射极电压并输出通过放大第三晶体管的发射极电压而获得的放大电压，其中第二晶体管24的基极电阻高于基极电阻 的第一晶体管23。

公开(公告)号：US07924102B2

公开(公告)日：2011-04-12

申请号：US12390648

申请日：2009-02-23

申请人： Jeffrey M. Hinrichs

发明人： Jeffrey M. Hinrichs

IPC分类号： H03K3/03

CPC分类号： H03K3/0322 ,  H03F3/45659 ,  H03F2203/45636 ,  H03F2203/45668 ,  H03F2203/45671

摘要： An oscillator includes a control circuit and a ring of symmetric load delay cells. Each delay cell includes two novel symmetric loads. Each load involves a level shift circuit and a diode-connected transistor coupled in parallel with a current source-connected transistor. The control circuit converts an oscillator input signal into bias control signals that in turn control the effective resistance of the symmetric loads such that delays through the delay cells are a function of the input signal. The control circuit uses a symmetric load replica in a control loop to control the level shift circuits of the delay cells such that the oscillating delay cell output signals have a constant amplitude. In a first advantageous aspect, due to the constant amplitude, the oscillator is operable over a wide frequency range. In a second advantageous aspect, the oscillator input signal to output signal oscillation frequency has a substantially linear relationship.

摘要翻译： 振荡器包括控制电路和对称负载延迟单元的环。 每个延迟单元包括两个新的对称负载。 每个负载涉及与电流源连接的晶体管并联耦合的电平移位电路和二极管连接的晶体管。 控制电路将振荡器输入信号转换成偏置控制信号，该偏置控制信号又控制对称负载的有效电阻，使得通过延迟单元的延迟是输入信号的函数。 控制电路使用控制回路中的对称负载复制来控制延迟单元的电平移位电路，使得振荡延迟单元输出信号具有恒定的幅度。 在第一有利的方面，由于恒定幅度，振荡器可在宽的频率范围内操作。 在第二有利的方面，振荡器输入信号到输出信号振荡频率具有基本上的线性关系。

公开(公告)号：US07436261B2

公开(公告)日：2008-10-14

申请号：US11723864

申请日：2007-03-22

申请人： Sawada Kazuyoshi

发明人： Sawada Kazuyoshi

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2203/45248 ,  H03F2203/45512 ,  H03F2203/45631 ,  H03F2203/45641 ,  H03F2203/45668 ,  H03F2203/45682

摘要： An operational amplifier includes: a differential amplifier circuit configured to receive an inverting input voltage (VIN−) and a non-inverting input voltage (VIN+); and an auxiliary circuit for improving a slew rate of an output voltage of the differential amplifier circuit, wherein when a voltage difference between the inverting input voltage (VIN−) and the non-inverting input voltage (VIN+) is less than a predetermined small voltage difference, an output terminal of the auxiliary circuit is disconnected from an output terminal of the differential amplifier circuit, and when the voltage difference exceeds the predetermined small voltage difference so that a voltage waveform is shifted to at least one direction, the voltage shift is accelerated by receiving/transferring a current from/to the output terminal of the differential amplifier circuit toward a shifting direction of an output voltage of the differential amplifier circuit.

摘要翻译： 运算放大器包括：差分放大器电路，被配置为接收反相输入电压（VIN-）和非反相输入电压（VIN +）; 以及用于提高差分放大器电路的输出电压的转换速率的辅助电路，其中当反相输入电压（VIN-）和非反相输入电压（VIN +）之间的电压差小于预定的小电压 不同之处在于，辅助电路的输出端子与差分放大电路的输出端断开，当电压差超过预定的小电压差使电压波形向至少一个方向移动时，电压偏移加速 通过从差分放大器电路的输出端子向差分放大器电路的输出电压的移位方向接收/传送电流。

公开(公告)号：US20060202721A1

公开(公告)日：2006-09-14

申请号：US11079711

申请日：2005-03-14

申请人： Anthony Partow ,  Ricky Jordanger

发明人： Anthony Partow ,  Ricky Jordanger

IPC分类号： H03K5/22

CPC分类号： H03K5/2481 ,  H03F3/45183 ,  H03F2200/78 ,  H03F2203/45008 ,  H03F2203/45078 ,  H03F2203/45088 ,  H03F2203/45101 ,  H03F2203/45112 ,  H03F2203/45626 ,  H03F2203/45642 ,  H03F2203/45668 ,  H03F2203/45678 ,  H03F2203/45681 ,  H03F2203/45732 ,  H03K5/003

摘要： A system and method is provided for extending the range of a common mode voltage of a differential comparator. In one embodiment, a differential comparator comprises an input stage with a negative voltage reference node, a first differential input coupled to a first differential pair transistor and operative to receive a first input signal, and a second differential input coupled to a second differential pair transistor and operative to receive a second input signal. The first input signal and the second input signal form a differential input signal. The differential comparator further comprises a common mode sensing circuit interconnected between the first differential input, the second differential input, and the negative voltage reference node. The common mode sensing circuit is operative to sense a common mode voltage of the differential input signal and set a voltage potential at the negative voltage reference node substantially equal to the sensed common mode voltage.

摘要翻译： 提供了一种用于扩展差分比较器的共模电压的范围的系统和方法。 在一个实施例中，差分比较器包括具有负电压参考节点的输入级，耦合到第一差分对晶体管并用于接收第一输入信号的第一差分输入和耦合到第二差分对晶体管的第二差分输入 并且用于接收第二输入信号。 第一输入信号和第二输入信号形成差分输入信号。 差分比较器还包括在第一差分输入，第二差分输入和负电压参考节点之间互连的共模感测电路。 共模感测电路用于检测差分输入信号的共模电压，并将负电压参考节点处的电压电位设置为基本上等于感测的共模电压。

公开(公告)号：US5521552A

公开(公告)日：1996-05-28

申请号：US469441

申请日：1995-06-06

申请人： James R. Butler

发明人： James R. Butler

IPC分类号： H03F3/30 ,  H03F3/45

CPC分类号： H03F3/3067 ,  H03F3/45121 ,  H03F2203/45668 ,  H03F2203/45722

摘要： A bipolar micro-power rail-to-rail operational amplifier has a low complexity output stage that provides a high ratio of load current to no load idle current. The output stage includes first and second output transistors of opposite conductivities whose current circuits are connected in series at the output terminal between high and low voltage supplies. A control transistor responds to the drive voltage at its base by modulating the base-emitter voltages of the first output transistor and a gain transistor in opposite directions to modulate their respective output and gain currents. A regenerative current source supplies current to the gain transistor by returning the gain current in a regenerative feedback loop to its emitter so that the current source idles at a low gain current but is capable of supplying much higher gain currents. A voltage element responds to the gain current by applying a control voltage to the base of the second output transistor so that the output transistors' output currents are unbalanced thereby generating an output current at the output terminal.

摘要翻译： 双极微功率轨至轨运算放大器具有低复杂度的输出级，提供高负载电流与无负载空闲电流的比率。 输出级包括具有相反电导率的第一和第二输出晶体管，其电流电路在高电压和低电压电源之间的输出端串联连接。 控制晶体管通过相反方向调制第一输出晶体管和增益晶体管的基极 - 发射极电压来响应其基极的驱动电压，以调制其相应的输出和增益电流。 再生电流源通过将再生反馈回路中的增益电流返回到其发射极来向增益晶体管提供电流，使得电流源以低增益电流空闲，但能够提供高得多的增益电流。 电压元件通过向第二输出晶体管的基极施加控制电压来响应于增益电流，使得输出晶体管的输出电流不平衡，从而在输出端产生输出电流。

公开(公告)号：US07795975B2

公开(公告)日：2010-09-14

申请号：US12038122

申请日：2008-02-27

申请人： Yu-Hsin Lin ,  Hsueh-Kun Liao

发明人： Yu-Hsin Lin ,  Hsueh-Kun Liao

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/3022 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45668

摘要： An amplifier is disclosed. An input transistor receives an input voltage. An impedance unit is coupled to a first electrode of the input transistor. A current source is coupled to a second electrode of the input transistor. A push-pull output circuit comprises a PMOS transistor and a NMOS transistor electrically connected in series to output an output voltage. The first electrode of the input transistor is coupled to a control terminal of the NMOS transistor. A level shifting unit is coupled between the first electrode of the input transistor and the push-pull output circuit, for shifting a voltage of the first electrode of the input transistor and providing a shifted voltage corresponding to the voltage of the first electrode of the input transistor to the control terminal of the PMOS transistor.

摘要翻译： 公开了放大器。 输入晶体管接收输入电压。 阻抗单元耦合到输入晶体管的第一电极。 电流源耦合到输入晶体管的第二电极。 推挽输出电路包括串联电连接以输出输出电压的PMOS晶体管和NMOS晶体管。 输入晶体管的第一电极耦合到NMOS晶体管的控制端。 电平移位单元耦合在输入晶体管的第一电极和推挽输出电路之间，用于移位输入晶体管的第一电极的电压，并提供与输入的第一电极的电压相对应的移位电压 晶体管连接到PMOS晶体管的控制端。

公开(公告)号：US20090212866A1

公开(公告)日：2009-08-27

申请号：US12038122

申请日：2008-02-27

申请人： Yu-Hsin Lin ,  Hsueh-Kun Liao

发明人： Yu-Hsin Lin ,  Hsueh-Kun Liao

IPC分类号： H03F3/18 ,  H03F3/16

CPC分类号： H03F3/45183 ,  H03F3/3022 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45668

摘要： An amplifier is disclosed. An input transistor receives an input voltage. An impedance unit is coupled to a first electrode of the input transistor. A current source is coupled to a second electrode of the input transistor. A push-pull output circuit comprises a PMOS transistor and a NMOS transistor electrically connected in series to output an output voltage. The first electrode of the input transistor is coupled to a control terminal of the NMOS transistor. A level shifting unit is coupled between the first electrode of the input transistor and the push-pull output circuit, for shifting a voltage of the first electrode of the input transistor and providing a shifted voltage corresponding to the voltage of the first electrode of the input transistor to the control terminal of the PMOS transistor.

摘要翻译： 公开了放大器。 输入晶体管接收输入电压。 阻抗单元耦合到输入晶体管的第一电极。 电流源耦合到输入晶体管的第二电极。 推挽输出电路包括串联电连接以输出输出电压的PMOS晶体管和NMOS晶体管。 输入晶体管的第一电极耦合到NMOS晶体管的控制端。 电平移位单元耦合在输入晶体管的第一电极和推挽输出电路之间，用于移位输入晶体管的第一电极的电压，并提供与输入的第一电极的电压相对应的移位电压 晶体管连接到PMOS晶体管的控制端。

公开(公告)号：US20090115527A1

公开(公告)日：2009-05-07

申请号：US12265361

申请日：2008-11-05

申请人： Chang-Shun Liu

发明人： Chang-Shun Liu

IPC分类号： H03F3/16

CPC分类号： H03F3/45183 ,  H03F1/086 ,  H03F3/3022 ,  H03F3/45192 ,  H03F2203/30015 ,  H03F2203/45526 ,  H03F2203/45626 ,  H03F2203/45668

摘要： The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, there is no need extra frequency compensating component for compensating the transistor of the output stage circuit, and to save circuit layout area and cost can be achieved by the present invention.

摘要翻译： 本发明涉及一种输出级电路及其运算放大器。 在输出级电路中，响应于从运算放大器中的放大电路输出的小信号，将晶体管的栅极中的一个耦合到偏置晶体管的栅极和电平移位器。 此外，偏置晶体管的栅极电压由电压产生电路控制，以控制输出级电路的晶体管的DC偏置。 因此，不需要用于补偿输出级电路的晶体管的额外的频率补偿分量，并且通过本发明可以实现节省电路布局面积和成本。

公开(公告)号：US20090015330A1

公开(公告)日：2009-01-15

申请号：US12195059

申请日：2008-08-20

申请人： Hiroyasu Morikawa ,  Masamichi Katada ,  Marie Nishinaka

发明人： Hiroyasu Morikawa ,  Masamichi Katada ,  Marie Nishinaka

IPC分类号： H03F3/45

CPC分类号： H03F3/45197 ,  H03F3/45201 ,  H03F2203/45288 ,  H03F2203/45356 ,  H03F2203/45471 ,  H03F2203/45652 ,  H03F2203/45668 ,  H03G1/0029 ,  H03G7/001

摘要： The variable transconductance circuit includes: a voltage-current conversion circuit for outputting a current signal linear with an input voltage signal; first and second MOS transistors for converting the current signal received to a square-root compressed voltage signal; and third and fourth MOS transistors for converting the square-root compressed voltage signal to a linear current signal. A bias current at the first and second MOS transistors and a bias current at the third and fourth MOS transistors are varied to control transconductance.

摘要翻译： 可变跨导电路包括：电压电流转换电路，用于输出与输入电压信号成线性的电流信号; 用于将接收的电流信号转换为平方根压缩电压信号的第一和第二MOS晶体管; 以及用于将平方根压缩电压信号转换为线性电流信号的第三和第四MOS晶体管。 改变第一和第二MOS晶体管的偏置电流以及第三和第四MOS晶体管的偏置电流以控制跨导。

公开(公告)号：US07463078B2

公开(公告)日：2008-12-09

申请号：US11623185

申请日：2007-01-15

申请人： Songtao Xu

发明人： Songtao Xu

IPC分类号： H03L5/00

CPC分类号： H03F3/45475 ,  H03F3/45183 ,  H03F2203/45101 ,  H03F2203/45134 ,  H03F2203/45138 ,  H03F2203/45511 ,  H03F2203/45641 ,  H03F2203/45652 ,  H03F2203/45668

摘要： An analog level-shifting differential amplifier for providing signal amplitude and/or common mode adjustment is disclosed. In one example, a receiver system may include a first amplification stage that is powered, for example, via an I/O power supply (e.g., VDDIO) and a second amplification stage that is powered, for example, via a core logic power supply (e.g., VDD). Arranged between the first and second amplification stages may be the analog level-shifting differential amplifier. The analog level-shifting differential amplifier may include a set of variable impedance elements for controlling the output common mode and output signal swing of the level-shifting differential amplifier.

摘要翻译： 公开了一种用于提供信号幅度和/或共模调整的模拟电平移位差分放大器。 在一个示例中，接收机系统可以包括例如经由I / O电源（例如，VDDIO）供电的第一放大级和例如经由核心逻辑电源供电的第二放大级 （例如，VDD）。 在第一和第二放大级之间布置可以是模拟电平移位差分放大器。 模拟电平移位差分放大器可以包括用于控制电平移位差分放大器的输出共模和输出信号摆幅的一组可变阻抗元件。