Methods and apparatuses for microelectronic assembly having a material with a variable viscosity around a MEMS device
    2.
    发明申请
    Methods and apparatuses for microelectronic assembly having a material with a variable viscosity around a MEMS device 有权
    用于微电子组件的方法和装置具有在MEMS器件周围具有可变粘度的材料

    公开(公告)号:US20060214246A1

    公开(公告)日:2006-09-28

    申请号:US11089906

    申请日:2005-03-24

    申请人: Jason Garcia

    发明人: Jason Garcia

    IPC分类号: H01L23/29 H01L21/00

    摘要: Various methods and apparatuses are described in which a micro-electro-mechanical systems (MEMS) device is encapsulated with a material having a variable viscosity with a viscosity value high enough to retard foreign material from contacting the MEMS device during an electronic package assembly process. The material having the variable viscosity may be affixed to a cavity area surrounding the MEMS device prior to an epoxy being dispensed onto the electronic package assembly. The temperature and pressure conditions of the electronic package assembly process may be controlled to ensure when the epoxy is dispensed that the material having the variable viscosity has a high enough viscosity value to retard foreign material from contacting the MEMS device during the electronic package assembly process.

    摘要翻译: 描述了各种方法和装置,其中微电子机械系统(MEMS)装置用具有可变粘度的材料包封,其粘度值足够高以在电子封装组装过程期间阻止异物接触MEMS装置。 具有可变粘度的材料可以在将环氧树脂分配到电子封装组件之前固定到围绕MEMS器件的空腔区域。 可以控制电子封装组装过程的温度和压力条件,以确保当分配环氧树脂时,具有可变粘度的材料具有足够高的粘度值,以在电子封装组装过程期间阻止异物接触MEMS器件。

    Die handling system
    4.
    发明申请
    Die handling system 有权
    模具处理系统

    公开(公告)号:US20060073632A1

    公开(公告)日:2006-04-06

    申请号:US10959931

    申请日:2004-10-06

    申请人: Jason Garcia

    发明人: Jason Garcia

    IPC分类号: H01L21/44

    摘要: A system may include singulation of a semiconductor wafer to separate a plurality of integrated circuit die that are integrated into the semiconductor wafer; coupling of a support to an integrated circuit substrate of one of the plurality of integrated circuit die, and decoupling of the one integrated circuit die from the singulated semiconductor wafer while the support is coupled to the integrated circuit substrate. According to some embodiments, a second side of the one integrated circuit die is not touched during the coupling and the decoupling, the second side being opposite to the integrated circuit substrate.

    摘要翻译: 系统可以包括半导体晶片的分离以分离集成到半导体晶片中的多个集成电路裸片; 将支撑件耦合到多个集成电路管芯中的一个集成电路管芯的集成电路基板,以及在支撑件耦合到集成电路基板的同时将单个集成电路管芯与分离的半导体晶片分离。 根据一些实施例,在耦合和解耦期间,一个集成电路管芯的第二侧不被接触,第二侧与集成电路衬底相对。

    Method of manufacturing a plurality of electronic assemblies
    6.
    发明申请
    Method of manufacturing a plurality of electronic assemblies 审中-公开
    制造多个电子组件的方法

    公开(公告)号:US20060019468A1

    公开(公告)日:2006-01-26

    申请号:US10897067

    申请日:2004-07-21

    IPC分类号: H01L21/78 H01L21/48 H01L21/50

    摘要: A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. Each electronic assembly has a respective die from a separated portion of the device wafer and a carrier substrate from a separated portion of the carrier wafer. The process of fabricating electronic assemblies is simplified and costs are reduced because the dies are connected to the carrier substrate at wafer level, i.e. before singulation. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively.

    摘要翻译: 提供一种制造多个电子设备的方法。 形成在器件晶片上的多个集成电路上的多个第一导电端子中的每一个连接到载体晶片上的多个第二导电端子中的相应一个,从而形成组合晶片组件。 组合晶片组件在集成电路之间分离以形成分离的电子组件。 每个电子组件具有来自器件晶片的分离部分的相应裸片和来自载体晶片的分离部分的载体衬底。 制造电子组件的过程被简化并且成本降低,因为模具以晶片级连接到载体衬底,即在分割之前。 组合晶片组件还允许底片填充材料被引入并在晶片级别固化并且在晶片级别使器件晶片变薄,而不需要单独的支撑衬底。 可以通过分别通过在器件和载体晶片中的电流通过第一和第二导体来测试器件晶片和载体晶片之间的对准。