公开(公告)号：US20130146986A1

公开(公告)日：2013-06-13

申请号：US13324740

申请日：2011-12-13

申请人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L27/092 ,  H01L27/088

CPC分类号： H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

摘要翻译： 提供半导体器件用于实现至少一个逻辑元件。 该半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 沟槽硅化物层将第一晶体管的源极或漏极之一电连接到第二晶体管的源极或漏极之一。

公开(公告)号：US09355910B2

公开(公告)日：2016-05-31

申请号：US13324740

申请日：2011-12-13

申请人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L21/70 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L27/118

CPC分类号： H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

摘要翻译： 提供半导体器件用于实现至少一个逻辑元件。 该半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 沟槽硅化物层将第一晶体管的源极或漏极之一电连接到第二晶体管的源极或漏极之一。

公开(公告)号：US08598633B2

公开(公告)日：2013-12-03

申请号：US13351101

申请日：2012-01-16

申请人： Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

摘要翻译： 半导体器件包括具有扩散区域的半导体衬底。 晶体管形成在扩散区内。 电力轨设置在扩散区域的外侧。 接触层设置在基板上方和电源轨下方。 通孔设置在接触层和电源轨之间以将接触层电连接到电源轨。 接触层包括设置在扩散区域外部的第一长度和从第一长度延伸到扩散区域并电连接到晶体管的第二长度。

公开(公告)号：US20190326219A1

公开(公告)日：2019-10-24

申请号：US16502521

申请日：2019-07-03

申请人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L23/535 ,  H01L29/08 ,  H01L27/092 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/285 ,  H01L27/02 ,  H01L21/768

摘要： A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

公开(公告)号：US20130181289A1

公开(公告)日：2013-07-18

申请号：US13351101

申请日：2012-01-16

申请人： Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L23/5286 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

摘要翻译： 半导体器件包括具有扩散区域的半导体衬底。 晶体管形成在扩散区内。 电力轨设置在扩散区域的外侧。 接触层设置在基板上方和电源轨下方。 通孔设置在接触层和电源轨之间以将接触层电连接到电源轨。 接触层包括设置在扩散区域外部的第一长度和从第一长度延伸到扩散区域并电连接到晶体管的第二长度。

公开(公告)号：US08581348B2

公开(公告)日：2013-11-12

申请号：US13324699

申请日：2011-12-13

申请人： Mahbub Rashed ,  Steven Soss ,  Jongwook Kye ,  Irene Y. Lin ,  James Benjamin Gullette ,  Chinh Nguyen ,  Jeff Kim ,  Marc Tarabbia ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Steven Soss ,  Jongwook Kye ,  Irene Y. Lin ,  James Benjamin Gullette ,  Chinh Nguyen ,  Jeff Kim ,  Marc Tarabbia ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L27/088 ,  H01L21/70 ,  H01L21/02

CPC分类号： H01L21/76895 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

摘要翻译： 提供半导体器件用于实现至少一个逻辑元件。 半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 CA层电连接到第一晶体管的源极或漏极中的至少一个。 CB层电连接到晶体管和CA层的至少一个栅极。

公开(公告)号：US20130146982A1

公开(公告)日：2013-06-13

申请号：US13324699

申请日：2011-12-13

申请人： Mahbub Rashed ,  Steven Soss ,  Jongwook Kye ,  Irene Y. Lin ,  James Benjamin Gullette ,  Chinh Nguyen ,  Jeff Kim ,  Marc Tarabbia ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Steven Soss ,  Jongwook Kye ,  Irene Y. Lin ,  James Benjamin Gullette ,  Chinh Nguyen ,  Jeff Kim ,  Marc Tarabbia ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L27/088

CPC分类号： H01L21/76895 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

摘要翻译： 提供半导体器件用于实现至少一个逻辑元件。 半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 CA层电连接到第一晶体管的源极或漏极中的至少一个。 CB层电连接到晶体管和CA层的至少一个栅极。