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    High-voltage oxide transistor and method of manufacturing the same
    2.
    发明授权
    High-voltage oxide transistor and method of manufacturing the same 有权
    高压氧化物晶体管及其制造方法

    公开(公告)号：US08698246B2

    公开(公告)日：2014-04-15

    申请号：US13547200

    申请日：2012-07-12

    Applicant: Sang-hun Jeon ,  Chang-jung Kim ,  I-hun Song

    Inventor： Sang-hun Jeon ,  Chang-jung Kim ,  I-hun Song

    IPC: H01L29/10 ,  H01L29/15 ,  H01L29/80 ,  H01L27/12 ,  H01L23/62 ,  H01L21/00 ,  H01L21/84 ,  H01L21/337

    CPC classification number: H01L29/42384 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

    Abstract: A high-voltage oxide transistor includes a substrate; a channel layer disposed on the substrate; a gate electrode disposed on the substrate to correspond to the channel layer; a source contacting a first side of the channel layer; and a drain contacting a second side of the channel layer, wherein the channel layer includes a plurality of oxide layers, and none of the plurality of oxide layers include silicon. The gate electrode may be disposed on or under the channel layer. Otherwise, the gate electrodes may be disposed respectively on and under the channel layer.

    Abstract translation: 高压氧化物晶体管包括基板; 设置在所述基板上的沟道层; 设置在所述基板上以对应于所述沟道层的栅电极; 源极，与所述沟道层的第一侧接触; 以及与沟道层的第二面接触的漏极，其中所述沟道层包括多个氧化物层，并且所述多个氧化物层中没有一个包括硅。 栅电极可以设置在沟道层上或下面。 否则，栅极电极可以分别设置在沟道层上和下面。

    Stacked memory device and method thereof
    4.
    发明授权
    Stacked memory device and method thereof 有权
    堆叠式存储器件及其方法

    公开(公告)号：US08547719B2

    公开(公告)日：2013-10-01

    申请号：US12588275

    申请日：2009-10-09

    Applicant: Jae-chul Park ,  Kee-won Kwon ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

    Inventor： Jae-chul Park ,  Kee-won Kwon ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

    IPC: G11C5/02

    CPC classification number: G11C5/02 ,  G11C5/143 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0023 ,  G11C2213/71

    Abstract: A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.

    Abstract translation: 堆叠存储器件包括多个存储器层，其中多个存储器层中的至少一个堆叠在多个存储器层中的另一个上，并且每个存储器层包括存储器单元阵列，第一有源电路单元配置 将至少一个存储器单元的地址信息分类并处理为垂直地址信息和水平地址信息，以及至少一个第二有源电路单元，配置为基于处理的信号为存储器单元中的至少一个生成存储器选择信号 由第一有源电路单元。

    ZnO based semiconductor devices and methods of manufacturing the same
    6.
    发明授权
    ZnO based semiconductor devices and methods of manufacturing the same 有权
    基于ZnO的半导体器件及其制造方法

    公开(公告)号：US08421070B2

    公开(公告)日：2013-04-16

    申请号：US12929324

    申请日：2011-01-14

    Applicant: Chang-jung Kim ,  I-hun Song ,  Dong-hun Kang ,  Young-soo Park

    Inventor： Chang-jung Kim ,  I-hun Song ,  Dong-hun Kang ,  Young-soo Park

    IPC: H01L29/12

    CPC classification number: H01L29/7869

    Abstract: A semiconductor device may include a composite represented by Formula 1 below as an active layer. x(Ga2O3).y(In2O3).z(ZnO)  Formula 1 wherein, about 0.75≦x/z≦about 3.15, and about 0.55≦y/z≦about 1.70. Switching characteristics of displays and driving characteristics of driving transistors may be improved by adjusting the amounts of a gallium (Ga) oxide and an indium (In) oxide mixed with a zinc (Zn) oxide and improving optical sensitivity.

    Abstract translation: 半导体器件可以包括由下面的式1表示的复合物作为有源层。 x（Ga 2 O 3）y（In 2 O 3）z（ZnO）式1其中约0.75＆lt; lE; x / z＆nlE;约3.15和约0.55≤n1E; y /z≤n1E;约1.70。 可以通过调节与锌（Zn）氧化物混合的镓（Ga）氧化物和铟（In））的量来提高驱动晶体管的开关特性并提高光学灵敏度。

    Oxide semiconductor transistors and methods of manufacturing the same
    7.
    发明授权
    Oxide semiconductor transistors and methods of manufacturing the same 有权
    氧化物半导体晶体管及其制造方法

    公开(公告)号：US08399882B2

    公开(公告)日：2013-03-19

    申请号：US12801500

    申请日：2010-06-11

    Applicant: Sang-hun Jeon ,  I-hun Song ,  Chang-jung Kim ,  Sung-ho Park

    Inventor： Sang-hun Jeon ,  I-hun Song ,  Chang-jung Kim ,  Sung-ho Park

    IPC: H01L29/12

    CPC classification number: H01L29/7869

    Abstract: Transistors and methods of manufacturing the same. A transistor may be an oxide thin film transistor (TFT) with a self-aligned top gate structure. The transistor may include a gate insulating layer between a channel region and a gate electrode that extends from two sides of the gate electrode. The gate insulating layer may cover at least a portion of source and drain regions.

    Abstract translation: 晶体管及其制造方法。 晶体管可以是具有自对准顶栅结构的氧化物薄膜晶体管（TFT）。 晶体管可以包括从栅电极的两侧延伸的沟道区和栅电极之间的栅极绝缘层。 栅绝缘层可以覆盖源区和漏区的至少一部分。

    Inverter, method of manufacturing the same, and logic circuit including the inverter
    8.
    发明授权
    Inverter, method of manufacturing the same, and logic circuit including the inverter 有权
    逆变器及其制造方法以及包括逆变器的逻辑电路

    公开(公告)号：US08383472B2

    公开(公告)日：2013-02-26

    申请号：US13067306

    申请日：2011-05-24

    Applicant: Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

    Inventor： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

    IPC: H01L21/336

    CPC classification number: H01L21/823807 ,  H01L27/0922 ,  H01L27/1225 ,  H01L27/1251

    Abstract: Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

    Abstract translation: 提供逆变器，逆变器的制造方法以及包括逆变器的逻辑电路。 反相器可以包括具有不同沟道层结构的第一晶体管和第二晶体管。 第一晶体管的沟道层可以包括下层和上层，并且第二晶体管的沟道层可以与下层和上层之一相同。 下层和上层中的至少一层可以是氧化物层。 逆变器可以是增强/耗尽型（E / D）型逆变器或互补型逆变器。

    LIGHT-SENSING APPARATUSES, METHODS OF DRIVING THE LIGHT-SENSING APPARATUSES, AND OPTICAL TOUCH SCREEN APPARATUSES INCLUDING THE LIGHT-SENSING APPARATUSES
    9.
    发明申请
    LIGHT-SENSING APPARATUSES, METHODS OF DRIVING THE LIGHT-SENSING APPARATUSES, AND OPTICAL TOUCH SCREEN APPARATUSES INCLUDING THE LIGHT-SENSING APPARATUSES 有权
    感光装置，驱动感光装置的方法，以及包括感光装置的光触控屏幕装置

    公开(公告)号：US20120327032A1

    公开(公告)日：2012-12-27

    申请号：US13435666

    申请日：2012-03-30

    Applicant: Sang-hun JEON ,  I-hun SONG ,  Seung-eon AHN ,  Chang-jung KIM ,  Young KIM

    Inventor： Sang-hun JEON ,  I-hun SONG ,  Seung-eon AHN ,  Chang-jung KIM ,  Young KIM

    IPC: G06F3/042 ,  H01L31/113 ,  H01L31/0264

    CPC classification number: H01L27/14609 ,  G06F3/042 ,  G06F2203/04103

    Abstract: Light-sensing apparatuses may include a light sensor transistor and a switching transistor in a light-sensing pixel, the transistors being oxide semiconductor transistors. In the light-sensing apparatus, the light sensor transistor and the switching transistor in the light-sensing pixel may be adjacently formed on one substrate, the switching transistor including a channel material that is relatively less light-sensitive than the light sensor transistor and is stable, and the light sensor transistor includes a channel material that is relatively light-sensitive. The light sensor transistor may include a transparent upper electrode on a surface of a channel, and a negative voltage may be applied to the transparent upper electrode, whereby a threshold voltage shift in a negative voltage direction may be prevented or reduced.

    Abstract translation: 光感测装置可以包括光感测像素中的光传感器晶体管和开关晶体管，该晶体管是氧化物半导体晶体管。 在感光装置中，光感测像素中的光传感器晶体管和开关晶体管可以相邻地形成在一个衬底上，该开关晶体管包括与光传感器晶体管相比较不光敏的沟道材料，并且是 并且光传感器晶体管包括相对光敏的通道材料。 光传感器晶体管可以在通道的表面上包括透明上电极，并且可以向透明上电极施加负电压，由此可以防止或减小负电压方向上的阈值电压偏移。

    Channel layers and semiconductor devices including the same
    10.
    发明授权
    Channel layers and semiconductor devices including the same 有权
    通道层和包括其的半导体器件

    公开(公告)号：US08232551B2

    公开(公告)日：2012-07-31

    申请号：US12458491

    申请日：2009-07-14

    Applicant: Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

    Inventor： Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

    IPC: H01L29/26

    CPC classification number: H01L29/7869 ,  H01L29/78696

    Abstract: Channel layers and semiconductor devices including the channel layers are disclosed. A channel layer may include a multi-layered structure. Layers forming the channel layer may have different carrier mobilities and/or carrier densities. The channel layer may have a double layered structure including a first layer and a second layer which may be formed of different oxides. Characteristics of the transistor may vary according to materials used to form the channel layers and/or thicknesses thereof.

    Abstract translation: 公开了包括沟道层的通道层和半导体器件。 沟道层可以包括多层结构。 形成沟道层的层可具有不同的载流子迁移率和/或载流子密度。 沟道层可以具有双层结构，其包括可由不同氧化物形成的第一层和第二层。 晶体管的特性可以根据用于形成沟道层的材料和/或其厚度而变化。

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