公开(公告)号：US08693296B2

公开(公告)日：2014-04-08

申请号：US12519691

申请日：2007-12-04

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： G11B7/00

CPC分类号： G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/10425 ,  G11B20/14 ,  G11B2020/1239 ,  G11B2020/1244 ,  G11B2020/1245 ,  G11B2220/2537 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L2207/50

摘要： A digital loop filter receives a phase error output from a phase comparator to generate a digital frequency value. This digital frequency value is converted into an analog voltage by a D/A converter, and VCO outputs a synchronizing dock of frequency corresponding to the voltage output from the D/A converter. The phase error output from a phase comparator is gain-corrected by a product of an output from the digital loop filter and a specific coefficient “A”, and delivered to digital loop filter. The phase error input to the digital loop filter is changed in proportion to the output clock frequency, whereby the PLL loop as whole linearly controls the loop characteristic depending on the output clock frequency.

摘要翻译： 数字环路滤波器接收从相位比较器输出的相位误差，以产生数字频率值。 该数字频率值由D / A转换器转换为模拟电压，VCO输出与D / A转换器输出的电压对应的频率同步基座。 来自相位比较器的相位误差输出由数字环路滤波器的输出与特定系数“A”的乘积进行增益校正，并传送到数字环路滤波器。 输入到数字环路滤波器的相位误差与输出时钟频率成比例地变化，由此PLL环路根据输出时钟频率线性地控制环路特性。

公开(公告)号：US08456977B2

公开(公告)日：2013-06-04

申请号：US13137967

申请日：2011-09-22

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： G11B7/00

CPC分类号： G11B20/1025 ,  G11B20/10046 ,  G11B2220/2562 ,  H03D2200/0086

摘要： A digital PLL (phase locked loop) circuit (and method thereof), includes an AAF (anti aliasing filter) that limits a frequency bandwidth of an input RF (radio frequency) signal on the basis of a given cutoff frequency, an ADC (analog to digital converter) that samples an output signal of the AAF on the basis of a given sampling frequency, a down converter that converts a data rate of the ADC, and a digital phase tracking unit that generates a synchronous clock signal from an output signal of the down converter on the basis of a given internal frequency. The cutoff frequency and the sampling frequency are fixed, respectively, even when a frequency bandwidth of the RF signal fluctuates. The down converter reduces the data rate according to an increase in the frequency bandwidth of the RF signal.

摘要翻译： 数字PLL（锁相环）电路（及其方法）包括基于给定截止频率来限制输入RF（射频）信号的频率带宽的AAF（抗混叠滤波器），ADC（模拟 数字转换器），其基于给定的采样频率对转换器的数据速率的下变频器进行采样，以及数字相位跟踪单元，该单位从ADC的输出信号产生同步时钟信号， 基于给定内部频率的下变频器。 即使当RF信号的频率带宽波动时，截止频率和采样频率分别是固定的。 降压转换器根据RF信号的频率带宽的增加来降低数据速率。

公开(公告)号：US20120087225A1

公开(公告)日：2012-04-12

申请号：US13137967

申请日：2011-09-22

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： H03L7/06 ,  G11B20/10 ,  H03D3/24

CPC分类号： G11B20/1025 ,  G11B20/10046 ,  G11B2220/2562 ,  H03D2200/0086

摘要： A digital PLL (phase locked loop) circuit (and method thereof), includes an AAF (anti aliasing filter) that limits a frequency bandwidth of an input RF (radio frequency) signal on the basis of a given cutoff frequency, an ADC (analog to digital converter) that samples an output signal of the AAF on the basis of a given sampling frequency, a down converter that converts a data rate of the ADC, and a digital phase tracking unit that generates a synchronous clock signal from an output signal of the down converter on the basis of a given internal frequency. The cutoff frequency and the sampling frequency are fixed, respectively, even when a frequency bandwidth of the RF signal fluctuates. The down converter reduces the data rate according to an increase in the frequency bandwidth of the RF signal.

摘要翻译： 数字PLL（锁相环）电路（及其方法）包括基于给定截止频率来限制输入RF（射频）信号的频率带宽的AAF（抗混叠滤波器），ADC（模拟 数字转换器），其基于给定的采样频率对转换器的数据速率的下变频器进行采样，以及数字相位跟踪单元，该单位从ADC的输出信号产生同步时钟信号， 基于给定内部频率的下变频器。 即使当RF信号的频率带宽波动时，截止频率和采样频率分别是固定的。 降压转换器根据RF信号的频率带宽的增加来降低数据速率。

公开(公告)号：US08004443B2

公开(公告)日：2011-08-23

申请号：US12524072

申请日：2008-01-07

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： H03M1/12

CPC分类号： G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10111 ,  G11B20/10212 ,  G11B20/10296 ,  G11B20/10425 ,  G11B20/10481 ,  G11B20/1403 ,  G11B20/1426 ,  G11B2220/2562

摘要： An information readout apparatus includes analog to digital converting means, equalizing means, interpolating means, maximum likelihood detecting means and PLL means. The analog to digital converting means converts a read signal read out from an optical disc medium, on which data is recorded with run length limited code that the shortest run length is 1, into a digital signal, and outputs the digital signal in synchronous with a first clock signal with a frequency which is N/M times of a channel frequency. At this time, N is an integer equal to or more than 2 and M is an integer meeting N/M>0.5. The equalizing means equalizes said digital signal to a previously specified partial response (PR) characteristic in synchronous with said first clock signal signal. The interpolating means converts N input data outputted from said equalizing means into M output data, and outputs output data in synchronous with a second clock signal with a frequency of 1/M times of the channel frequency. The maximum likelihood detecting means converts the output data outputted from said interpolation means into an M-bit detection data, and outputs said detection data in synchronous with said second clock signal signal. The PLL means generates said first clock signal and said second clock signal based on said read signal.

摘要翻译： 信息读取装置包括模数转换装置，均衡装置，内插装置，最大似然检测装置和PLL装置。 模数转换装置将从最短游程长度为1的游程长度限制码记录有数据的光盘介质读出的读取信号转换成数字信号，并与数字信号同步输出 第一时钟信号，其频率是信道频率的N / M倍。 此时，N是等于或大于2的整数，M是满足N / M> 0.5的整数。 均衡装置将所述数字信号与所述第一时钟信号信号同步地将先前指定的部分响应（PR）特性相等。 内插装置将从所述均衡装置输出的N个输入数据转换为M个输出数据，并以与信道频率的1 / M倍的频率的第二时钟信号同步地输出输出数据。 最大似然检测装置将从所述插值装置输出的输出数据转换成M位检测数据，并且与所述第二时钟信号信号同步地输出所述检测数据。 PLL装置基于所述读取信号产生所述第一时钟信号和所述第二时钟信号。

公开(公告)号：US20100091624A1

公开(公告)日：2010-04-15

申请号：US12448533

申请日：2007-12-11

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： G11B23/00

CPC分类号： H03L7/08 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10222 ,  G11B2220/2537 ,  H03L2207/50

摘要： An A/D converter samples a read signal in synchrony with a system clock sclk having a fixed frequency, to perform an A/D conversion. A fluctuation compensator is configured as an internal-feedback-type compensation filter, and suppresses fluctuation of a digital signal output from the A/D converter. A digital PLL uses an interpolator to generate, by interpolation, a sampled value of the read signal at a timing in synchrony with a channel frequency, and uses NCO to generate a synchronizing clock and an interpolated-phase signal that is fed back to the interpolator. A binarization circuit binarizes the read signal based on the interpolated value output from the interpolator. The frequency characteristic of the fluctuation compensator is controlled based on the frequency value output from the loop filter.

摘要翻译： A / D转换器与具有固定频率的系统时钟sclk同步地对读取信号进行采样，以执行A / D转换。 波动补偿器被配置为内部反馈型补偿滤波器，并且抑制从A / D转换器输出的数字信号的波动。 数字PLL使用内插器以与通道频率同步的定时通过内插生成读取信号的采样值，并且使用NCO来产生反馈到内插器的同步时钟和内插相位信号 。 二值化电路基于从内插器输出的内插值二值化读取信号。 基于从环路滤波器输出的频率值来控制波动补偿器的频率特性。

公开(公告)号：US07091895B2

公开(公告)日：2006-08-15

申请号：US10957385

申请日：2004-10-01

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： H03M1/00

CPC分类号： G11B20/1403 ,  G11B2020/1239 ,  H03L7/0807 ,  H03L7/091 ,  H03L7/0991 ,  H03L2207/50 ,  H03M1/361

摘要： An A/D converter includes a low-bit resolution A/D which converts an input signal into a digital value of 4 bits or less, and a low-pass digital filter which suppresses a high-frequency-band component in an output from the low-bit resolution A/D, and extracts phase information contained in the input signal as amplitude information. A digital PLL circuit and information recording apparatus are also disclosed.

摘要翻译： A / D转换器包括将输入信号转换为4位或更小的数字值的低位分辨率A / D，以及抑制来自该位置的输出中的高频带分量的低通数字滤波器 低位分辨率A / D，并且将包含在输入信号中的相位信息提取为振幅信息。 还公开了数字PLL电路和信息记录装置。

公开(公告)号：US20050073454A1

公开(公告)日：2005-04-07

申请号：US10957385

申请日：2004-10-01

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： G11B20/10 ,  H03L7/08 ,  H03L7/091 ,  H03L7/099 ,  H03M1/36 ,  H03M1/64 ,  H03M1/12

CPC分类号： G11B20/1403 ,  G11B2020/1239 ,  H03L7/0807 ,  H03L7/091 ,  H03L7/0991 ,  H03L2207/50 ,  H03M1/361

摘要： An A/D converter includes a low-bit resolution A/D which converts an input signal into a digital value of 4 bits or less, and a low-pass digital filter which suppresses a high-frequency-band component in an output from the low-bit resolution A/D, and extracts phase information contained in the input signal as amplitude information. A digital PLL circuit and information recording apparatus are also disclosed.

摘要翻译： A / D转换器包括将输入信号转换为4位或更小的数字值的低位分辨率A / D，以及抑制来自该位置的输出中的高频带分量的低通数字滤波器 低位分辨率A / D，并且将包含在输入信号中的相位信息提取为振幅信息。 还公开了数字PLL电路和信息记录装置。

公开(公告)号：US06249553B1

公开(公告)日：2001-06-19

申请号：US08989889

申请日：1997-12-12

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： H03D100

CPC分类号： H03M13/6343 ,  H03M13/4107 ,  H03M13/6508 ,  H04L25/03248 ,  H04L25/064

摘要： In a direct current fluctuation level detecting circuit, differences between sample values and a Viterbi detector reference level are summed in an interval of n samples using path selection information and minimum path metric information, which are detected in a Viterbi detector, and the function is completed through further operations in a branch difference generating circuit and an AS circuit. A direct current level V0 can be detected by a further process where an AS circuit output is multiplied by 1/n in a multiplier and the multiplication result is stored in a register. A timing generating circuit controls latching of the register and clearing of a path difference value with a cycle of n samples. A detected direct current level V0 is fed back to an input to compensate a direct current level fluctuation in an adaptive manner.

摘要翻译： 在直流波动电平检测电路中，使用在维特比检测器中检测到的路径选择信息和最小路径量度信息，在n个样本的间隔中将样本值和维特比检测器参考电平之间的差值相加，并且功能完成 通过在分支差产生电路和AS电路中的进一步操作。 可以通过进一步的处理来检测直流电平V0，其中AS电路输出在乘法器中乘以1 / n，乘法结果存储在寄存器中。 定时发生电路控制寄存器的锁存和以n个采样的周期清除路径差值。 检测到的直流电平V0被反馈到输入端，以自适应方式补偿直流电平波动。

公开(公告)号：US5781590A

公开(公告)日：1998-07-14

申请号：US844660

申请日：1997-04-21

申请人： Masato Shiokawa ,  Hiromi Honma

发明人： Masato Shiokawa ,  Hiromi Honma

IPC分类号： G11B20/10 ,  H03H17/00 ,  H04B3/04 ,  H04L25/48 ,  H04L27/06

CPC分类号： G11B20/10101 ,  G11B20/10009 ,  G11B20/10111

摘要： A PRML (Partial Response Maximum Likelihood) signal processing apparatus for both MP (Mark Position) recorded medium and ME (Mark Edge) recorded medium. The apparatus has a PR (Partial Response) equalizer to which the reproduction signal from the medium is inputted, a folded back value calculation circuit for folding back an input signal thereto with a predetermined level, and a Viterbi detector having a path memory and performing a Viterbi detection. The path memory is constructed based on a structure of a trellis for a signal recorded by the MP recording. In case of the MP recorded medium, the equalizer transfer characteristics and the reference amplitude both for the MP recording are set to the PR equalizer and the Viterbi detector, respectively, and the output of the PR equalizer is directly supplied to the Viterbi detector. On the other hand, in case of the MP recorded medium, the equalizer transfer characteristics and the reference amplitude both for the ME recording are set, and the output of the PR equalizer is supplied to the Viterbi detector via the folded back value calculation circuit.

摘要翻译： 用于MP（Mark Position）记录介质和ME（Mark Edge）记录介质的PRML（部分响应最大似然）信号处理装置。 该装置具有输入来自媒体的再现信号的PR（部分响应）均衡器，用于以预定电平折叠输入信号的折返值计算电路，以及具有路径存储器并执行 维特比检测。 基于由MP记录记录的信号的网格结构构建路径存储器。 在MP记录介质的情况下，均衡器传送特性和用于MP记录的参考幅度分别被设置到PR均衡器和维特比检测器，并且PR均衡器的输出被直接提供给维特比检测器。 另一方面，在MP记录介质的情况下，设置ME记录的均衡器传送特性和参考幅度，并且通过折返值计算电路将PR均衡器的输出提供给维特比检测器。

公开(公告)号：US5661713A

公开(公告)日：1997-08-26

申请号：US562060

申请日：1995-11-22

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： G11B20/14 ,  G11B7/00 ,  G11B7/005 ,  G11B11/105 ,  G11B20/10

CPC分类号： G11B20/10203 ,  G11B20/10037 ,  G11B11/10515 ,  G11B11/1053 ,  G11B7/005

摘要： A level sensor circuit compares a threshold level from a threshold value generator circuit with that of an input sampling signal to create a binarized pulsated signal. A change point detector circuit detects a change point of binary information indicated by the input pulsates signal or positions before and after the change point and thereby sends a change point detection signal(s) to a threshold level generator circuit. The threshold level generator circuit extracts from the sampling signals only ones at points of time when the change point detection signal is inputted from the change point detector circuit and then averages the extracted sampling signals with respect to time to generate a threshold level.

摘要翻译： 电平传感器电路将来自阈值发生器电路的阈值电平与输入采样信号的阈值电平进行比较，以产生二值化的脉动信号。 改变点检测器电路检测由输入脉动信号或变化点之前和之后的位置指示的二进制信息的变化点，从而向阈值电平发生器电路发送变化点检测信号。 阈值电平发生器电路仅在来自变化点检测器电路输入变化点检测信号的时间点的采样信号中提取采样信号，然后对提取的采样信号相对于时间进行平均以产生阈值电平。