A digital PLL (phase locked loop) circuit (and method thereof), includes an AAF (anti aliasing filter) that limits a frequency bandwidth of an input RF (radio frequency) signal on the basis of a given cutoff frequency, an ADC (analog to digital converter) that samples an output signal of the AAF on the basis of a given sampling frequency, a down converter that converts a data rate of the ADC, and a digital phase tracking unit that generates a synchronous clock signal from an output signal of the down converter on the basis of a given internal frequency. The cutoff frequency and the sampling frequency are fixed, respectively, even when a frequency bandwidth of the RF signal fluctuates. The down converter reduces the data rate according to an increase in the frequency bandwidth of the RF signal.