公开(公告)号：US5781590A

公开(公告)日：1998-07-14

申请号：US844660

申请日：1997-04-21

申请人： Masato Shiokawa ,  Hiromi Honma

发明人： Masato Shiokawa ,  Hiromi Honma

IPC分类号： G11B20/10 ,  H03H17/00 ,  H04B3/04 ,  H04L25/48 ,  H04L27/06

CPC分类号： G11B20/10101 ,  G11B20/10009 ,  G11B20/10111

摘要： A PRML (Partial Response Maximum Likelihood) signal processing apparatus for both MP (Mark Position) recorded medium and ME (Mark Edge) recorded medium. The apparatus has a PR (Partial Response) equalizer to which the reproduction signal from the medium is inputted, a folded back value calculation circuit for folding back an input signal thereto with a predetermined level, and a Viterbi detector having a path memory and performing a Viterbi detection. The path memory is constructed based on a structure of a trellis for a signal recorded by the MP recording. In case of the MP recorded medium, the equalizer transfer characteristics and the reference amplitude both for the MP recording are set to the PR equalizer and the Viterbi detector, respectively, and the output of the PR equalizer is directly supplied to the Viterbi detector. On the other hand, in case of the MP recorded medium, the equalizer transfer characteristics and the reference amplitude both for the ME recording are set, and the output of the PR equalizer is supplied to the Viterbi detector via the folded back value calculation circuit.

摘要翻译： 用于MP（Mark Position）记录介质和ME（Mark Edge）记录介质的PRML（部分响应最大似然）信号处理装置。 该装置具有输入来自媒体的再现信号的PR（部分响应）均衡器，用于以预定电平折叠输入信号的折返值计算电路，以及具有路径存储器并执行 维特比检测。 基于由MP记录记录的信号的网格结构构建路径存储器。 在MP记录介质的情况下，均衡器传送特性和用于MP记录的参考幅度分别被设置到PR均衡器和维特比检测器，并且PR均衡器的输出被直接提供给维特比检测器。 另一方面，在MP记录介质的情况下，设置ME记录的均衡器传送特性和参考幅度，并且通过折返值计算电路将PR均衡器的输出提供给维特比检测器。

公开(公告)号：US08085639B2

公开(公告)日：2011-12-27

申请号：US12448533

申请日：2007-12-11

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： G11B7/00

CPC分类号： H03L7/08 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10222 ,  G11B2220/2537 ,  H03L2207/50

摘要： An A/D converter samples a read signal in synchrony with a system clock sclk having a fixed frequency, to perform an A/D conversion. A fluctuation compensator is configured as an internal-feedback-type compensation filter, and suppresses fluctuation of a digital signal output from the A/D converter. A digital PLL uses an interpolator to generate, by interpolation, a sampled value of the read signal at a timing in synchrony with a channel frequency, and uses NCO to generate a synchronizing clock and an interpolated-phase signal that is fed back to the interpolator. A binarization circuit binarizes the read signal based on the interpolated value output from the interpolator. The frequency characteristic of the fluctuation compensator is controlled based on the frequency value output from the loop filter.

摘要翻译： A / D转换器与具有固定频率的系统时钟sclk同步地对读取信号进行采样，以执行A / D转换。 波动补偿器被配置为内部反馈型补偿滤波器，并且抑制从A / D转换器输出的数字信号的波动。 数字PLL使用内插器以与通道频率同步的定时通过内插生成读取信号的采样值，并且使用NCO来产生反馈到内插器的同步时钟和内插相位信号 。 二值化电路基于从内插器输出的内插值二值化读取信号。 基于从环路滤波器输出的频率值来控制波动补偿器的频率特性。

公开(公告)号：US07072264B2

公开(公告)日：2006-07-04

申请号：US10337378

申请日：2003-01-07

申请人： Hiromi Honma ,  Kinji Kayanuma

发明人： Hiromi Honma ,  Kinji Kayanuma

IPC分类号： G11B7/00

CPC分类号： G11B20/1403 ,  G11B7/0053 ,  G11B20/10425 ,  G11B27/24 ,  H03L7/081 ,  H03L7/091 ,  H03L7/0994

摘要： A VCO, which good temperature characteristics, high frequency accuracy, and high phase accuracy is provided as an LSI, without making its master clock frequency operate the VCO high. The VCO includes a digital VCO, a phase modulator, and a frequency band limiting element. The digital VCO outputs an oscillating frequency clock and a phase difference lower than an output cycle resolution at the same timing as the output of the oscillating frequency clock. The phase modulator makes side-band components of the output from the digital VCO move from positions near the fundamental frequency to farther bands by modulating the phase of the output from the digital VCO based on the phase difference.

摘要翻译： 作为LSI提供了具有良好的温度特性，高频精度和高相位精度的VCO，而不使其主时钟频率高于VCO。 VCO包括数字VCO，相位调制器和频带限制元件。 数字VCO在与振荡频率时钟的输出相同的定时输出振荡频率时钟和低于输出周期分辨率的相位差。 相位调制器通过基于相位差调制来自数字VCO的输出的相位，使来自数字VCO的输出的边带分量从靠近基本频率的位置移动到更远的频带。

公开(公告)号：US06671244B2

公开(公告)日：2003-12-30

申请号：US09746879

申请日：2000-12-22

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： G11B509

CPC分类号： H04L7/0029 ,  G11B20/10009 ,  H04L7/0334

摘要： In an information detecting circuit, an equalizer equalizes an output from an A/D converter as an A/D converting information. A first interpolation circuit generates an interpolating value. A delay circuit delays the A/D converting information with a delay quantity equivalent to an output delay quantity of the equalizer. A second interpolation circuit generates an interpolating value. An interpolating position generating circuit produces an interpolating position information for generating an interpolating value synchronized in phase with the channel clock and supplies the interpolating position information into the first interpolation circuit and the second interpolation circuit. A binary encoder converts the output of the first interpolation circuit. A tap coefficient controller generates a tap coefficient from interpolating value outputs of the first and second interpolations. A rate correcting circuit converts the tap coefficient to be fed-back to the equalizer.

摘要翻译： 在信息检测电路中，均衡器将来自A / D转换器的输出作为A / D转换信息进行均衡。 第一插值电路产生内插值。 延迟电路以等于均衡器的输出延迟量的延迟量来延迟A / D转换信息。 第二插值电路产生内插值。 内插位置产生电路产生用于产生与通道时钟同相同步的内插值的内插位置信息，并将内插位置信息提供给第一内插电路和第二内插电路。 二进制编码器转换第一内插电路的输出。 抽头系数控制器通过内插第一和第二内插的值输出来产生抽头系数。 速率校正电路将要反馈的抽头系数转换成均衡器。

公开(公告)号：US5991914A

公开(公告)日：1999-11-23

申请号：US801570

申请日：1997-02-18

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： G06F11/10 ,  H03M13/12

CPC分类号： H04L7/0332 ,  H04L7/0334

摘要： In a clock recovery circuit, an input data sequence is sampled in response to clock pulses produced by a voltage-controlled oscillator and data samples are produced. Branch metrics are produced to represent errors of the data samples from reference levels which the input data sequence assumes when the clock pulses are either advanced or delayed by a predetermined phase with respect to optimum timing of the input data sequence. Corresponding to transition states which the branch metrics assume when the clock pulses are advanced by the predetermined phase, a first set of path metrics is produced and corresponding to transition states which the branch metrics assume when the clock pulses are delayed by the predetermined phase, a second set of path metrics is produced. First and second minimum path metrics are selected from the first and second sets of path metrics, respectively, and a differential minimum path metric representative of the difference between the first and second minimum path metrics is produced. Successive differential minimum path metrics are integrated and the V.C.O. is controlled with the integrated path metrics.

摘要翻译： 在时钟恢复电路中，响应由压控振荡器产生的时钟脉冲对输入数据序列进行采样，并产生数据采样。 产生分支度量，以便当相对于输入数据序列的最佳定时将时钟脉冲提前或延迟预定相位时，从输入数据序列所采用的参考电平来表示数据样本的误差。 对应于当时钟脉冲提前预定相位时分支度量假设的转换状态，产生第一组路径度量，并且对应于当时钟脉冲被延迟预定相位时分支度量假定的过渡状态， 产生第二组路径度量。 分别从第一和第二组路径度量中选择第一和第二最小路径度量，并且产生表示第一和第二最小路径度量之间的差异的差分最小路径量度。 连续差分最小路径度量被集成，并且V.C.O. 由集成路径度量进行控制。

公开(公告)号：US20110051576A1

公开(公告)日：2011-03-03

申请号：US12801427

申请日：2010-06-08

申请人： Tetsuo Ashizawa ,  Hiromi Honma

发明人： Tetsuo Ashizawa ,  Hiromi Honma

IPC分类号： G11B20/10 ,  G11B27/36

CPC分类号： G11B20/10333 ,  G11B20/10046 ,  G11B20/10212 ,  G11B20/10425 ,  G11B2020/1287 ,  G11B2220/2537

摘要： An LPP detection unit detects an LPP from a wobble signal. A correction unit obtains a difference set by performing processing of calculating a difference in signal level between an LPP-present sync pattern portion and a non-LPP sync pattern portion having the same polarity, and executes correction on an RF signal at a timing when the LPP is detected, by using the difference set. The LPP-present sync pattern portion is a sync pattern portion obtained when the LPP is detected at the timing of the sync pattern portion positioned at the head of a sync frame of the RF signal. The non-LPP sync pattern portion is a sync pattern portion obtained when no LPP is detected at the timing of the sync pattern portion of the sync frame. In the case of reproducing information recorded on a DVD-R/RW optical disk, the occurrence of errors due to the effect of the LPP can be reduced.

公开(公告)号：US20100103791A1

公开(公告)日：2010-04-29

申请号：US12524024

申请日：2008-01-25

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： G11B20/10

CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/18 ,  G11B2220/2537

摘要： An offset corrector of an information readout apparatus receives a digital signal DRF output from an A/D converter, and performs offset correction. The offset corrector is capable of switching between a level-correction operation that corrects the offset so that the DC level of the shortest period signal included in the readout signal assumes a zero amplitude reference and a HPF operation that matches the level of the readout signal with the zero amplitude reference. The offset corrector corrects the offset in the level correction operation during a normal reproduction, and switches to the HPF operation for offset correction when a defect judgment unit detects a defective area. The information readout apparatus is stable and has a superior performance without a symmetry deviation if there occurs a waveform fluctuation caused by a defect etc.

摘要翻译： 信息读出装置的偏移校正器接收从A / D转换器输出的数字信号DRF，进行偏移校正。 偏移校正器能够在校正偏移的电平校正操作之间切换，使得包括在读出信号中的最短周期信号的DC电平呈现零幅度参考，并且与读出信号的电平匹配的HPF操作与 零幅度参考。 偏移校正器在正常再现期间校正电平校正操作中的偏移，并且当缺陷判断单元检测到缺陷区域时，切换到用于偏移校正的HPF操作。 信息读出装置是稳定的，如果发生由缺陷等引起的波形波动，则具有优异的性能而没有对称偏差。

公开(公告)号：US20100054716A1

公开(公告)日：2010-03-04

申请号：US12524072

申请日：2008-01-07

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： H04N5/00 ,  H03M1/12

CPC分类号： G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10111 ,  G11B20/10212 ,  G11B20/10296 ,  G11B20/10425 ,  G11B20/10481 ,  G11B20/1403 ,  G11B20/1426 ,  G11B2220/2562

摘要： An information readout apparatus includes analog to digital converting means, equalizing means, interpolating means, maximum likelihood detecting means and PLL means. The analog to digital converting means converts a read signal read out from an optical disc medium, on which data is recorded with run length limited code that the shortest run length is 1, into a digital signal, and outputs the digital signal in synchronous with a first clock signal with a frequency which is N/M times of a channel frequency. At this time, N is an integer equal to or more than 2 and M is an integer meeting N/M>0.5. The equalizing means equalizes said digital signal to a previously specified partial response (PR) characteristic in synchronous with said first clock signal signal. The interpolating means converts N input data outputted from said equalizing means into M output data, and outputs output data in synchronous with a second clock signal with a frequency of 1/M times of the channel frequency. The maximum likelihood detecting means converts the output data outputted from said interpolation means into an M-bit detection data, and outputs said detection data in synchronous with said second clock signal signal. The PLL means generates said first clock signal and said second clock signal based on said read signal.

摘要翻译： 信息读取装置包括模数转换装置，均衡装置，内插装置，最大似然检测装置和PLL装置。 模数转换装置将从最短游程长度为1的游程长度限制码记录有数据的光盘介质读出的读取信号转换成数字信号，并与数字信号同步输出 第一时钟信号，其频率是信道频率的N / M倍。 此时，N是等于或大于2的整数，M是满足N / M> 0.5的整数。 均衡装置将所述数字信号与所述第一时钟信号信号同步地将先前指定的部分响应（PR）特性相等。 内插装置将从所述均衡装置输出的N个输入数据转换为M个输出数据，并以与信道频率的1 / M倍的频率的第二时钟信号同步地输出输出数据。 最大似然检测装置将从所述插值装置输出的输出数据转换成M位检测数据，并且与所述第二时钟信号信号同步地输出所述检测数据。 PLL装置基于所述读取信号产生所述第一时钟信号和所述第二时钟信号。

公开(公告)号：US20090097371A1

公开(公告)日：2009-04-16

申请号：US12282280

申请日：2007-03-06

申请人： Hiromi Honma ,  Yasuo Ogasawara

发明人： Hiromi Honma ,  Yasuo Ogasawara

IPC分类号： G11B7/00

CPC分类号： G11B20/1816 ,  G11B7/0948 ,  G11B20/10009 ,  G11B20/10027 ,  G11B20/10046 ,  G11B20/10425 ,  G11B2020/1239 ,  G11B2220/2537

摘要： An optical disc device includes an optical head section and a regularity monitoring circuit. The optical head section generates a wobble signal indicating wobbling of a track formed on a recording surface of an optical disc medium based on a reflected light reflected by the optical disc medium. The regularity monitoring circuit judges an existence or absence of a defect on the optical disc medium based on a difference between the wobble signal and a signal indicating the wobble under a normal condition.

摘要翻译： 光盘装置包括光头部分和规则性监视电路。 光头部分基于由光盘介质反射的反射光产生指示形成在光盘介质的记录表面上的轨迹的摆动的摆动信号。 基于摆动信号和表示正常条件下的摆动的信号之间的差异，规律性监视电路判断光盘介质上存在或不存在缺陷。

公开(公告)号：US06788484B2

公开(公告)日：2004-09-07

申请号：US10020850

申请日：2001-12-07

申请人： Hiromi Honma

发明人： Hiromi Honma

IPC分类号： G11B509

CPC分类号： G11B20/10009 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10055 ,  G11B20/10083 ,  G11B20/10111 ,  G11B20/10222 ,  G11B20/1403 ,  H03L7/091

摘要： A PLL circuit is disclosed which extracts phase difference information of a high S/N ratio from a readout signal uses the phase difference information for PLL control. An A/D converter samples the input signal to produce a digital signal. A pattern string detector identifies a type of an input pattern string formed from a plurality of successive sample values successively outputted from the A/D converter and outputs pattern string identification information which indicates an identification result. A phase difference generator outputs phase difference information which indicates a phase error of the output of the A/D converter based on the pattern string identification information and the output of the A/D converter. A loop filter, a D/A converter and a voltage controlled oscillator generate a clock signal from the phase difference information to control the sampling timing of the A/D converter.

摘要翻译： 公开了从读出信号中提取高S / N比的相位差信息的PLL电路使用PLL控制的相位差信息。 A / D转换器对输入信号进行采样以产生数字信号。 图案字符串检测器识别由从A / D转换器连续输出的多个连续取样值形成的输入图案串的类型，并输出表示识别结果的图案串识别信息。 相位差发生器基于模式串识别信息和A / D转换器的输出，输出表示A / D转换器的输出的相位误差的相位差信息。 环路滤波器，D / A转换器和压控振荡器从相位差信息产生时钟信号，以控制A / D转换器的采样定时。