A digital loop filter receives a phase error output from a phase comparator to generate a digital frequency value. This digital frequency value is converted into an analog voltage by a D/A converter, and VCO outputs a synchronizing dock of frequency corresponding to the voltage output from the D/A converter. The phase error output from a phase comparator is gain-corrected by a product of an output from the digital loop filter and a specific coefficient “A”, and delivered to digital loop filter. The phase error input to the digital loop filter is changed in proportion to the output clock frequency, whereby the PLL loop as whole linearly controls the loop characteristic depending on the output clock frequency.