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    Testing vias and contracts in integrated circuit
    1.
    发明授权
    Testing vias and contracts in integrated circuit 有权
    测试集成电路中的通孔和合同

    公开(公告)号：US07046026B2

    公开(公告)日：2006-05-16

    申请号：US10897500

    申请日：2004-07-23

    申请人： Tai-An Chao ,  Zicheng Gary Ling ,  Shihcheng Hsueh

    发明人： Tai-An Chao ,  Zicheng Gary Ling ,  Shihcheng Hsueh

    IPC分类号： G01R31/26

    CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test arrangement is designed to test whether one in a chain of vias or contacts has abnormally high resistance. The arrangement contains a plurality of via or contact chains and a plurality of decoders. The chains are switchably connected to a resistance measurement device. Each decoder has a unique address such that it will generate a control signal when a predetermined address is address thereon. The control signal is used to close a switch, which connect one of the chains to the resistance measurement device. By sequentially applying different addresses to the decoders, the resistance of the chains can be individually measured.

    摘要翻译： 测试装置被设计用于测试通孔或接触链中的一个是否具有异常高的电阻。 该装置包括多个通孔或接触链和多个解码器。 链可切换地连接到电阻测量装置。 每个解码器具有唯一的地址，使得当预定地址是地址时，它将产生控制信号。 控制信号用于关闭开关，将开关连接到电阻测量装置。 通过对解码器顺序地应用不同的地址，可以单独地测量链的电阻。

    Exposure correction based on reflective index for photolithographic process control
    2.
    发明授权
    Exposure correction based on reflective index for photolithographic process control 有权
    基于光刻过程控制反射指数的曝光校正

    公开(公告)号：US06482573B1

    公开(公告)日：2002-11-19

    申请号：US09492216

    申请日：2000-01-27

    申请人： Jayendra D. Bhakta ,  Zicheng Gary Ling ,  Weizhong Wang ,  Warren T. Yu ,  Eric Kent

    发明人： Jayendra D. Bhakta ,  Zicheng Gary Ling ,  Weizhong Wang ,  Warren T. Yu ,  Eric Kent

    IPC分类号： G03C556

    CPC分类号： G03F7/70625 ,  Y10S430/151

    摘要： Critical dimension variation of photolithographically formed features on a semiconductor substrate is reduced by measuring the reflectivity of a photoresist layer and an underlying layer, such as a polysilicon layer, and adjusting the exposure level of the photoresist in accordance with the measured reflectivity. This allows precise control of feature width on the photoresist, which in turn allows precision etching of the underlying layer to accurately form a feature, such as a gate electrode.

    摘要翻译： 通过测量光致抗蚀剂层和诸如多晶硅层的下层的反射率，并根据所测量的反射率来调整光致抗蚀剂的曝光水平，可减少半导体衬底上的光刻形成特征的临界尺寸变化。 这允许对光致抗蚀剂上的特征宽度的精确控制，这又允许精确地蚀刻下层以精确地形成特征，例如栅电极。

    Active mask exposure compensation of underlying nitride thickness variation to reduce critical dimension (CD) variation
    3.
    发明授权
    Active mask exposure compensation of underlying nitride thickness variation to reduce critical dimension (CD) variation 有权
    主动掩模曝光补偿底层氮化物厚度变化以减少临界尺寸（CD）变化

    公开(公告)号：US06368762B1

    公开(公告)日：2002-04-09

    申请号：US09667573

    申请日：2000-09-22

    申请人： Zicheng Gary Ling

    发明人： Zicheng Gary Ling

    IPC分类号： G03F900

    CPC分类号： G03F7/2022 ,  H01L21/0274

    摘要： The CD variation of semiconductor devices on a wafer due to the variation in thickness of the underlying nitride layer is corrected by varying the lithographic exposure level as a function of the nitride layer thickness. Embodiments include decreasing the exposure level in areas where the nitride layer is relatively thicker.

    摘要翻译： 通过改变作为氮化物层厚度的函数的光刻曝光水平来校正由于下面的氮化物层的厚度变化导致的晶片上的半导体器件的CD变化。 实施例包括在氮化物层相对较厚的区域中降低曝光水平。

    Nitride disposable spacer to reduce mask count in CMOS transistor formation
    4.
    发明授权
    Nitride disposable spacer to reduce mask count in CMOS transistor formation 有权
    通过使用氮化物一次性间隔物来形成CMOS以减少掩模计数的方法

    公开(公告)号：US06218224B1

    公开(公告)日：2001-04-17

    申请号：US09276725

    申请日：1999-03-26

    申请人： Todd Lukanc ,  Raymond T. Lee ,  Zicheng Gary Ling

    发明人： Todd Lukanc ,  Raymond T. Lee ,  Zicheng Gary Ling

    IPC分类号： H01L218238

    CPC分类号： H01L21/823864

    摘要： Semiconductor devices of different conductivity types with optimized junction locations are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, sidewall spacers on side surfaces of the gates, and nitride disposable spacers on the sidewall spacers. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the nitride disposable spacers on the sidewall spacers on the unmasked gates removed, and lightly or moderately doped source/drain extension implants of the second impurity type formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining nitride disposable spacers removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using nitride disposable spacers, the critical masking steps for source/drain ion implantation are reduced to two, thereby reducing production costs and increasing manufacturing throughput. By employing sidewall spacers, impurities are prevented from being implanted at the edges of the gates. Thus, when source/drain junctions are formed, as by heating and diffusing the implanted impurities, they are advantageously located proximal to the gate edges, and not under the gates, thereby improving device performance.

    摘要翻译： 具有优化的连接位置的不同导电类型的半导体器件使用最少数量的临界掩模形成在半导体衬底上。 实施例包括在半导体衬底的主表面上形成导电栅极，在栅极侧表面上的侧壁间隔物和侧壁间隔物上的氮化物一次性间隔物。 然后在主要表面的浇口和部分上形成光致抗蚀剂掩模，以便植入第一导电类型的杂质。 然后在衬底中形成第二杂质类型的中等或重的源极/漏极注入，去除未屏蔽的栅极上的侧壁间隔物上的氮化物一次性间隔物，并且形成第二杂质类型的轻或中等掺杂的源极/漏极延伸植入物 底物。 然后去除第一掩模，并且在主表面的先前未覆盖的浇口和注入部分上形成第二光致抗蚀剂掩模。 然后形成具有第一导电类型的杂质的中等或重的源极/漏极植入物，去除剩余的氮化物一次性间隔物，并形成第一导电类型的轻微或中等掺杂的源极/漏极延伸植入物。 通过使用氮化物一次性间隔件，用于源极/漏极离子注入的关键掩模步骤减少到两个，从而降低生产成本并提高制造生产能力。 通过使用侧壁间隔物，防止杂质被植入门的边缘。 因此，当形成源极/漏极结时，通过加热和扩散植入的杂质，它们有利地位于栅极边缘附近，而不在栅极下方，从而提高器件性能。

    Amorphous silicon disposable spacer to reduce mask count in CMOS transistor formation
    5.
    发明授权
    Amorphous silicon disposable spacer to reduce mask count in CMOS transistor formation 有权
    非晶硅一次性间隔物，以减少CMOS晶体管形成中的掩模数量

    公开(公告)号：US06214655B1

    公开(公告)日：2001-04-10

    申请号：US09277161

    申请日：1999-03-26

    申请人： Raymond T. Lee ,  Zicheng Gary Ling

    发明人： Raymond T. Lee ,  Zicheng Gary Ling

    IPC分类号： H01L218238

    CPC分类号： H01L21/823864

    摘要： Semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable amorphous silicon spacers on the sidewalls of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the disposable spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining disposable spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using disposable spacers, the critical masking steps for source/drain ion implantation can be reduced to two, thereby reducing production costs and increasing manufacturing throughput.

    摘要翻译： 使用最少数量的临界掩模，在半导体衬底上形成不同导电类型的半导体器件。 实施例包括在半导体衬底的主表面上形成导电栅极和在栅极的侧壁上的一次性非晶硅间隔物。 然后在主要表面的浇口和部分上形成光致抗蚀剂掩模，以便植入第一导电类型的杂质。 然后在衬底中形成第二杂质类型的中等或重的源/漏植入物，然后去除未屏蔽的栅极上的一次性间隔物，并且在衬底中形成第二杂质类型的轻度或中等掺杂的源极/漏极延伸植入物 。 然后去除第一掩模，并且在主表面的先前未覆盖的浇口和注入部分上形成第二光致抗蚀剂掩模。 然后形成具有第一导电类型的杂质的中等或重的源极/漏极植入物，剩余的一次性间隔物被去除，并形成第一导电类型的轻度或中等掺杂的源极/漏极延伸植入物。 通过使用一次性间隔件，用于源/漏离子注入的关键掩蔽步骤可以减少到两个，从而降低生产成本并提高制造生产能力。

    Method and apparatus for connecting sink off set from sewer
    6.
    发明授权
    Method and apparatus for connecting sink off set from sewer 有权
    将下水道与下水道连接的方法和装置

    公开(公告)号：US07596865B1

    公开(公告)日：2009-10-06

    申请号：US10981955

    申请日：2004-11-05

    申请人： Gary Ling ,  Simon Maung

    发明人： Gary Ling ,  Simon Maung

    IPC分类号： B23P17/00

    CPC分类号： F16L19/065 ,  Y10T29/49428 ,  Y10T29/4943 ,  Y10T29/49826

    摘要： An apparatus and method for retrofitting a sink drain to a sewer pipe. A connector tube is provided with a preset curve that is cut at a selected location on the connector to provide a connection between the waste tee connector of a sewer line to a “P” connector. A “circularizing” tool is provided which shapes an elliptical end of a tube cut on a curve to a circle that telescopes into the nipple of a waste tube connector.

    摘要翻译： 一种用于将水槽排水口改造到下水道管道的装置和方法。 连接器管设置有在连接器上的选定位置切割的预设曲线，以提供下水道线的废气T形连接器与“P”连接器之间的连接。 提供了一种“圆化”工具，其将在曲线上切割的管的椭圆形端部形成为望远镜到废料管连接器的接头中的圆形。

    Method of generating an IC mask using a reduced database
    9.
    发明授权
    Method of generating an IC mask using a reduced database 有权
    使用简化数据库生成IC掩模的方法

    公开(公告)号：US06868537B1

    公开(公告)日：2005-03-15

    申请号：US10082991

    申请日：2002-02-25

    申请人： Jonathan J. Ho ,  Xin X. Wu ,  Zicheng Gary Ling ,  Jan L. de Jong

    发明人： Jonathan J. Ho ,  Xin X. Wu ,  Zicheng Gary Ling ,  Jan L. de Jong

    IPC分类号： G03F1/14 ,  G06F17/50

    CPC分类号： G03F1/36 ,  G03F1/68 ,  G06F17/5068 ,  G06F2217/12

    摘要： For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.

    摘要翻译： 对于具有重复结构的IC设备，生成用于制作掩模层的数据库的方法从描述层中的至少一个重复元素的分层数据库开始，围绕重复元素的骨架以及关于在哪里定位的指令 重复骨骼内的元素。 该数据库被修改以产生具有光学邻近校正（OPC）的数据库，用于衍射通过掩模并在IC层上曝光光致抗蚀剂的光的衍射。 使用关于如何将经修改的数据库分割以形成在OPC之后仍然相同的重复元素的指令，包含非重复元素的掩码框架以及用于放置 骨骼中的重复元素。 因此，所得到的掩码数据库小于包含所有重复元素副本的掩码数据库。

    Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer
    10.
    发明授权
    Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer 失效
    制造具有氮化物一次性间隔物的超浅结CMOS晶体管的方法

    公开(公告)号：US06551870B1

    公开(公告)日：2003-04-22

    申请号：US09686352

    申请日：2000-10-10

    申请人： Zicheng Gary Ling ,  James Chiang

    发明人： Zicheng Gary Ling ,  James Chiang

    IPC分类号： H01L218238

    CPC分类号： H01L21/823864 ,  H01L29/6659

    摘要： A method of developing a transistor, such as a complimentary MOS (CMOS) transistor, that includes lightly doped drain (LDD) regions which uses disposable spacers, and includes the step of adding an oxide spacer etch after a disposable nitride spacer removal and between source/drain implant and LDD implant. Because of this additional step, an ultra shallow LDD implant can be achieved. Moreover, uniformity of the depth of the junction is improved as the non-uniformity of the screen/liner oxide is eliminated.

    摘要翻译： 一种开发诸如补偿MOS（CMOS）晶体管的晶体管的方法，其包括使用一次性间隔物的轻掺杂漏极（LDD）区域，并且包括在一次性氮化物间隔物去除之后和在源极之间添加氧化物间隔物蚀刻的步骤 漏极植入和LDD植入。 由于这个附加步骤，可以实现超浅LDD植入。 此外，由于屏幕/衬垫氧化物的不均匀性被消除，结点深度的均匀性得到改善。