公开(公告)号：US20130020615A1

公开(公告)日：2013-01-24

申请号：US13188789

申请日：2011-07-22

Applicant: Su Chen Fan ,  David Horak ,  Sivananda K. Kanakasabapathy

Inventor： Su Chen Fan ,  David Horak ,  Sivananda K. Kanakasabapathy

IPC: H01L21/28 ,  H01L29/80

CPC classification number: H01L21/28 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/78

Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

Abstract translation: 一种方法包括在衬底的暴露部分和设置在衬底上的栅极堆叠上沉积虚拟填充材料，去除虚拟填充材料的部分以暴露衬底的部分，在衬底的暴露部分上形成间隔材料层 ，虚拟填充材料和栅极堆叠，去除间隔物材料层的部分以暴露衬底和虚拟填充材料的部分，在间隔材料，衬底和栅极堆叠的暴露部分上沉积介电层 去除所述介电层的部分以暴露所述间隔物材料的部分，去除所述间隔物材料的暴露部分以暴露所述基底的部分并且限定所述电介质层中的至少一个腔，以及在所述至少一个腔中沉积导电材料 。

公开(公告)号：US20110098318A1

公开(公告)日：2011-04-28

申请号：US12985579

申请日：2011-01-06

Applicant: Peter Albert Palmer ,  Ivan David Horak

Inventor： Peter Albert Palmer ,  Ivan David Horak

IPC: A61K31/4709 ,  A61P35/00

CPC classification number: A61K45/06 ,  A61K31/00 ,  A61K31/138 ,  A61K31/4709 ,  A61K31/4745 ,  A61K2300/00

Abstract: The present invention relates to the use of farnesyl protein transferase inhibitors for preparing pharmaceutical compositions for treating advanced breast cancer.

Abstract translation: 本发明涉及法呢基蛋白转移酶抑制剂用于制备用于治疗晚期乳腺癌的药物组合物的用途。

公开(公告)号：US20080099844A1

公开(公告)日：2008-05-01

申请号：US11969320

申请日：2008-01-04

Applicant: Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Leathen Shi

Inventor： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Leathen Shi

IPC: H01L29/786

CPC classification number: H01L29/045 ,  H01L21/76254 ,  H01L21/823807 ,  H01L27/1203

Abstract: A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.

Abstract translation: 绝缘体上半导体衬底及其制造方法。 所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向， 第一晶体方向与第二晶体方向不同。

公开(公告)号：US20080001225A1

公开(公告)日：2008-01-03

申请号：US11307294

申请日：2006-01-31

Applicant: Toshiharu Furukawa ,  Steven Holmes ,  David Horak ,  Charles Koburger

Inventor： Toshiharu Furukawa ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

Abstract: A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

Abstract translation: finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是在基底的相邻表面上，使得间隔层不完全覆盖 半导体鳍片 可以使用侧向生长方法制造其它微电子结构。

公开(公告)号：US20070241409A1

公开(公告)日：2007-10-18

申请号：US11764571

申请日：2007-06-18

Applicant: Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

Inventor： Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/76237 ,  H01L21/26533 ,  H01L21/76213 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/1087 ,  H01L29/78

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

Abstract translation: 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该半导体结构包括成形修饰的隔离区，其形成在通常在制造本体CMOS器件的衬底的两个掺杂阱之间的沟槽中。 成形改进的隔离区域可以包括沟槽的加宽的电介质填充部分，其可以可选地包括分隔两个掺杂阱之间的损伤区域的沟槽的附近损伤区域或狭窄的电介质填充部分。 也可以通过在沟槽中的沟槽基底和介电填料之间提供晶格不匹配的层来抑制闩锁。

公开(公告)号：US20070241408A1

公开(公告)日：2007-10-18

申请号：US11759981

申请日：2007-06-08

Applicant: Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

Inventor： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

IPC: H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

Abstract: A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

Abstract translation: CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

公开(公告)号：US20070215874A1

公开(公告)日：2007-09-20

申请号：US11378492

申请日：2006-03-17

Applicant: Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam

Inventor： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam

IPC: H01L23/58

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/528 ,  H01L2224/06 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.

Abstract translation: 一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。 第一和第二结构被嵌套，使得亚光刻线以平行方式设置在宽度内，并且第一结构的接触着陆段被设置在相对于子平版印刷线的相对侧的相对侧 第二结构的接触着陆段。 用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。

公开(公告)号：US20070184588A1

公开(公告)日：2007-08-09

申请号：US11735075

申请日：2007-04-13

Applicant: Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

Inventor： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC: H01L21/84

CPC classification number: H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

Abstract: A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

Abstract translation: 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

公开(公告)号：US20060267086A1

公开(公告)日：2006-11-30

申请号：US11140780

申请日：2005-05-31

Applicant: Toshijaru Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam ,  Gerhard Meijer

Inventor： Toshijaru Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Chung Lam ,  Gerhard Meijer

IPC: H01L29/76

CPC classification number: H01L27/101 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  Y10S438/90

Abstract: Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.

公开(公告)号：US20060169972A1

公开(公告)日：2006-08-03

申请号：US10906016

申请日：2005-01-31

Applicant: Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

Inventor： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

IPC: H01L29/06

CPC classification number: H01L27/0688 ,  B82Y10/00 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823487 ,  H01L27/0705 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/057 ,  Y10S977/938

Abstract: A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate electrode of a FET, or an emitter, collector, or base of a bipolar transistor. A method of forming the inventive hybrid semiconductor structure having at least one shared node between the vertical carbon nanotube transistor and the horizontal semiconductor device is also provided.

Abstract translation: 提供一种混合半导体结构，其包括水平半导体器件和垂直碳纳米管晶体管，其中垂直碳纳米管晶体管和水平半导体器件具有至少一个共享节点。 至少一个共享节点可以包括例如FET的漏极，源极或栅极电极，或双极晶体管的发射极，集电极或基极。 还提供了形成本发明的混合半导体结构的方法，该结构在竖直碳纳米管晶体管和水平半导体器件之间具有至少一个共享节点。