公开(公告)号：US09905658B2

公开(公告)日：2018-02-27

申请号：US14090327

申请日：2013-11-26

Applicant: Darrell G. Hill ,  Stephen H. Kilgore ,  Craig A. Gaw

Inventor： Darrell G. Hill ,  Stephen H. Kilgore ,  Craig A. Gaw

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/49 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/402 ,  H01L29/2003 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66462 ,  H01L29/7787

Abstract: An embodiment of a transistor includes a semiconductor substrate, spaced-apart source and drain electrodes coupled to the semiconductor substrate, a gate electrode coupled to the semiconductor substrate between the source and drain electrodes, a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate, and a field plate structure over the dielectric layer, wherein the field plate structure includes a gold-containing material and one or more migration inhibiting materials.

公开(公告)号：US09362198B2

公开(公告)日：2016-06-07

申请号：US14249538

申请日：2014-04-10

Applicant: Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L M Mahalingam

Inventor： Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L M Mahalingam

IPC: H01L31/102 ,  H01L23/367 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/04 ,  H01L21/28 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L23/373 ,  H01L21/042 ,  H01L21/0475 ,  H01L21/28 ,  H01L21/32051 ,  H01L21/762 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/04026 ,  H01L2224/29026 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

Abstract translation: 半导体器件的实施例包括半导体衬底，其包括主体衬底和上表面，有源区域，半导体衬底中的由凹陷表面局部限定的衬底开口，以及设置在半导体衬底上的导热层 其在有源区域内在凹入表面和半导体衬底的一部分之间延伸。 制造半导体器件的方法包括限定有源区域，在有源区域中的沟道上形成栅电极，在栅电极的相对侧上的有源区域中形成源电极和漏电极，蚀刻栅电极的衬底开口 所述半导体衬底由所述凹陷表面部分地限定，并且在所述半导体衬底上沉积导热层，所述导热层在所述沟道上在所述凹陷表面和所述半导体衬底的一部分之间延伸。

公开(公告)号：US20120175777A1

公开(公告)日：2012-07-12

申请号：US13005240

申请日：2011-01-12

Applicant: Darrell G. Hill ,  Bruce M. Green

Inventor： Darrell G. Hill ,  Bruce M. Green

IPC: H01L23/52 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: An electronic device (50) having a conductive substrate via (70) extending between a conductor (39) on a rear face (22) and a conductor (58) over the front surface (23) of the substrate (21) includes a multi-layered etch-stop (56, 56-2) beneath the front surface conductor (58). The etch-stop (56, 56-2) permits use of a single etchant to penetrate both the substrate (21) and any overlying semiconductor (44) and/or dielectric (34) without attacking the overlying front surface conductor (58). This is especially important when the semiconductor (44) and dielectric (34) are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop (56) is preferably a stack (63, 73) of N≧2 pairs (62-i) of sub-layers (62-i1, 62-i2) in either order, where a first sub-layer (62-i1) comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer (62-i2) comprises etch resistant material (e.g., Ni). In a further embodiment, where the device (50) includes field effect transistors (52) having feedback sensitive control gates (30), the etch-stop material (56) is advantageously used to form gate shields (76).

Abstract translation: 具有在背面（22）上的导体（39）与衬底（21）的前表面（23）之间的导体（58）之间延伸的导电衬底通孔（70）的电子器件（50）包括多 在前表面导体（58）下面的层间蚀刻停止（56,56-2）。 蚀刻停止（56,56-2）允许使用单个蚀刻剂来穿透基板（21）和任何上覆的半导体（44）和/或电介质（34），而不会攻击上覆的前表面导体（58）。 当半导体（44）和电介质（34）如此薄以至于在蚀刻期间达到这些区域时阻止改变蚀刻剂时，这尤其重要。 蚀刻停止（56）优选地是以任何顺序的N≥2对（62-i）子层（62-i1,62-i2）的堆叠（63,73），其中第一子层 62-i1）包括应力释放和/或粘附促进材料（例如Ti），并且第二子层（62-i2）包括耐蚀刻材料（例如Ni）。 在另一实施例中，在器件（50）包括具有反馈敏感控制栅极（30）的场效应晶体管（52）的情况下，蚀刻停止材料（56）有利地用于形成栅极屏蔽（76）。

公开(公告)号：US07642182B2

公开(公告)日：2010-01-05

申请号：US11972475

申请日：2008-01-10

Applicant: Agni Mitra ,  Darrell G. Hill ,  Karthik Rajagopalan ,  Adolfo C. Reyes

Inventor： Agni Mitra ,  Darrell G. Hill ,  Karthik Rajagopalan ,  Adolfo C. Reyes

IPC: H01L21/44

CPC classification number: H01L23/62 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/413 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.

Abstract translation: 为集成无源器件（IPD）的ESD保护提供了方法和设备。 该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。 当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。 当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。 本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。

公开(公告)号：US07335955B2

公开(公告)日：2008-02-26

申请号：US11300710

申请日：2005-12-14

Applicant: Agni Mitra ,  Darrell G. Hill ,  Karthik Rajagopalan ,  Adolfo C. Reyes

Inventor： Agni Mitra ,  Darrell G. Hill ,  Karthik Rajagopalan ,  Adolfo C. Reyes

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/413 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.

Abstract translation: 为集成无源器件（IPD）的ESD保护提供了方法和设备。 该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。 当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。 当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。 本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。

公开(公告)号：US20080039025A1

公开(公告)日：2008-02-14

申请号：US11833360

申请日：2007-08-03

Applicant: Marcus R. Ray ,  Darrell G. Hill ,  Ricardo A. Uscola

Inventor： Marcus R. Ray ,  Darrell G. Hill ,  Ricardo A. Uscola

IPC: H04B1/38

CPC classification number: H04B1/0475 ,  H04B1/0458

Abstract: A transceiver includes a harmonic termination circuit that receives a tunable harmonic voltage from a power amplifier control. The harmonic termination circuit includes a variable capacitor that is capable of adjusting its capacitance in response to the tunable harmonic termination voltage to achieve at least two modes of operation. The at least two modes of operation may be EDGE mode and GSM mode. In this embodiment, the harmonic termination circuit allows for linearity specifications of EDGE to be met, while not degrading the efficiency of the transceiver when operating in GSM mode. In one embodiment, the harmonic termination circuit further includes an inductive element in series with the variable capacitor.

Abstract translation: 收发器包括从功率放大器控制器接收可调谐谐波电压的谐波终端电路。 谐波终端电路包括可变电容器，其可以响应于可调谐谐波终端电压来调整其电容以实现至少两种操作模式。 至少两种操作模式可以是EDGE模式和GSM模式。 在本实施例中，谐波终端电路允许满足EDGE的线性规格，同时在GSM模式下工作时不降低收发器的效率。 在一个实施例中，谐波终端电路还包括与可变电容器串联的电感元件。

公开(公告)号：US06798064B1

公开(公告)日：2004-09-28

申请号：US09614794

申请日：2000-07-12

Applicant: Haldane S. Henry ,  Darrell G. Hill ,  Colby G. Rampley

Inventor： Haldane S. Henry ,  Darrell G. Hill ,  Colby G. Rampley

IPC: H01L2348

CPC classification number: H01L23/5221 ,  H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic component includes a substrate (110) and an airbridge (890) located over the substrate. The airbridge has at least a first layer and a second layer over the first layer. The airbridge is electrically conductive where the first layer of the airbridge is less resistive than the second layer of the airbridge.

Abstract translation: 电子部件包括位于基板上方的基板（110）和空气桥（890）。 空中桥梁在第一层上具有至少第一层和第二层。 空中桥梁是导电的，其中空中桥梁的第一层比空中桥梁的第二层电阻较小。

公开(公告)号：US6023336A

公开(公告)日：2000-02-08

申请号：US984223

申请日：1997-12-03

Applicant: Darrell G. Hill

Inventor： Darrell G. Hill

IPC: H01L21/68 ,  G01B11/00

CPC classification number: H01L21/68 ,  H01L21/681 ,  H01L2224/8113

Abstract: A method and apparatus for accurate automated alignment of semiconductor chips (12,14) or thin-film networks includes forming a plurality of vias (16-19,22-25) in each integrated circuit element in respective locations, and moving the integrated circuit elements to bring the corresponding vias into alignment. In one embodiment, the integrated circuit elements (12,14) are moved by inserting a plurality of spindles (36-39) into respective vias in the integrated circuit elements to align the integrated circuit elements. In another embodiment, the integrated circuit elements (40,42) are moved by providing a source of light (48) on one side of the integrated circuit elements and a light sensor (50) on another side of the integrated circuit elements, and moving the integrated circuit elements to maximize the amount of light traversing the vias (44,46). To enable precision alignment of the integrated circuit elements, the vias may be formed with diameter less than 50 .mu.m.

Abstract translation: 用于半导体芯片（12,14）或薄膜网络的精确自动对准的方法和装置包括在各个位置中在每个集成电路元件中形成多个通孔（16-19,22-25），并且移动集成电路 元件使相应的通孔对齐。 在一个实施例中，集成电路元件（12,14）通过将多个主轴（36-39）插入到集成电路元件中的相应过孔中而移动，以对准集成电路元件。 在另一个实施例中，集成电路元件（40,42）通过在集成电路元件的一侧上提供光源（48）和在集成电路元件的另一侧上的光传感器（50）而移动，并且移动 集成电路元件以使穿过通孔（44,46）的光量最大化。 为了实现集成电路元件的精确对准，通孔可以形成为直径小于50μm。

公开(公告)号：US5515562A

公开(公告)日：1996-05-14

申请号：US265403

申请日：1994-06-24

Applicant: Kenneth A. Miller ,  Darrell G. Hill ,  Shelly Perpich

Inventor： Kenneth A. Miller ,  Darrell G. Hill ,  Shelly Perpich

IPC: A61G13/00 ,  A61G13/12

CPC classification number: A61G13/0036

Abstract: The present invention provides for perineal and sacral padding of a patient undergoing surgical procedures using manipulation or traction of the patient's lower extremities.

Abstract translation: 本发明提供了使用患者下肢的操纵或牵引进行外科手术的患者的会阴和骶骨填充。

公开(公告)号：US5330932A

公开(公告)日：1994-07-19

申请号：US999072

申请日：1992-12-31

Applicant: William U. Liu ,  Shou-Kong Fan ,  Timothy S. Henderson ,  Darrell G. Hill

Inventor： William U. Liu ,  Shou-Kong Fan ,  Timothy S. Henderson ,  Darrell G. Hill

IPC: H01L29/205 ,  H01L21/306 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737 ,  H01L21/20

CPC classification number: H01L29/66318 ,  H01L21/30612 ,  H01L21/30621 ,  Y10S148/011

Abstract: In one form of the invention, a method is disclosed for removing portions of successive layers of GaAs 34 and GaInP 32 comprising the steps of: performing an anisotropic reactive ion etch on the GaAs layer; and performing an isotropic wet etch on the GaInP layer, whereby a mesa formed as a result of the reactive ion etch and the wet etch has substantially vertical sidewalls, and further whereby GaInP/GaAs structures having dimensions of less than approximately 3.0 .mu.m may be fabricated.

Abstract translation: 在本发明的一种形式中，公开了一种用于去除GaAs 34和GaInP 32的连续层的部分的方法，包括以下步骤：在GaAs层上执行各向异性反应离子蚀刻; 并且在GaInP层上进行各向同性的湿蚀刻，由此由反应离子蚀刻和湿蚀刻形成的台面具有基本垂直的侧壁，并且进一步地，尺寸小于约3.0μm的GaInP / GaAs结构可以是 制造。