知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

26 records (took 0.028 seconds)

    Methods for using isotopically enriched levels of dopant gas compositions in an ion implantation process
    1.
    发明授权
    Methods for using isotopically enriched levels of dopant gas compositions in an ion implantation process 有权
    在离子注入工艺中使用掺杂气体组合物的同位素浓度水平的方法

    公开(公告)号：US08883620B1

    公开(公告)日：2014-11-11

    申请号：US13869456

    申请日：2013-04-24

    Applicant: Ashwini K. Sinha ,  Ching I Li

    Inventor： Ashwini K. Sinha ,  Ching I Li

    IPC: H01L21/425 ,  H01L21/265 ,  H01J27/02

    CPC classification number: H01J27/02 ,  H01J37/302 ,  H01J37/3171 ,  H01J2237/006 ,  H01J2237/08 ,  H01L21/26506 ,  H01L21/2658

    Abstract: A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified levels.

    Abstract translation: 本文提供了一种使用富集和高度富集的掺杂气体的新方法，其消除了终端用户目前遇到的问题，即能够实现与离子注入这种掺杂气体相关的工艺优点。 对于规定范围内的给定流速，在离子源的总功率水平降低的情况下操作，以减少富集的掺杂气体与其相应的非富集或较小浓度的掺杂气体相比的离子化效率。 源极丝的温度也降低，从而在使用富含氟的掺杂气体时减轻氟蚀刻和离子源短路的不利影响。 总功率的降低水平与较低的离子化效率和较低的离子源温度相结合可以相互协调地相互作用，以改善和延长离子源寿命，同时有利地保持不能接受地偏离先前合格水平的束流。

    MANUFACTURING METHOD FOR METAL GATE
    2.
    发明申请
    MANUFACTURING METHOD FOR METAL GATE 有权
    金属门的制造方法

    公开(公告)号：US20130023098A1

    公开(公告)日：2013-01-24

    申请号：US13184572

    申请日：2011-07-18

    Applicant: Po-Cheng Huang ,  Kuo-Chih Lai ,  Ching-I Li ,  Yu-Shu Lin ,  Ya-Jyuan Hung ,  Yen-Liang Lu ,  Yu-Wen Wang ,  Hsin-Chih Yu

    Inventor： Po-Cheng Huang ,  Kuo-Chih Lai ,  Ching-I Li ,  Yu-Shu Lin ,  Ya-Jyuan Hung ,  Yen-Liang Lu ,  Yu-Wen Wang ,  Hsin-Chih Yu

    IPC: H01L21/336

    CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833

    Abstract: A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

    Abstract translation: 金属栅极的制造方法包括提供具有形成在其上的电介质层和多晶硅层的基板，多晶硅层，在多晶硅层上形成保护层，在保护层上形成图案化的硬掩模，进行第一蚀刻工艺 蚀刻保护层和多晶硅层，以在衬底上形成具有第一高度的虚拟栅极，形成覆盖图案化硬掩模和伪栅极的多层介电结构，去除伪栅极以在衬底上形成栅极沟槽， 以及在所述栅极沟槽中形成具有第二高度的金属栅极。 金属栅极的第二高度基本上等于虚拟栅极的第一高度。

    Method of fabricating an NMOS transistor
    3.
    发明申请
    Method of fabricating an NMOS transistor 有权
    制造NMOS晶体管的方法

    公开(公告)号：US20120083090A1

    公开(公告)日：2012-04-05

    申请号：US12897771

    申请日：2010-10-04

    Applicant: Chen-Hua Tsai ,  Po-Jui Liao ,  Tzu-Feng Kuo ,  Ching-I Li ,  Cheng-Tzung Tsai

    Inventor： Chen-Hua Tsai ,  Po-Jui Liao ,  Tzu-Feng Kuo ,  Ching-I Li ,  Cheng-Tzung Tsai

    IPC: H01L21/336

    CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/66628 ,  H01L29/7834

    Abstract: A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.

    Abstract translation: 形成SiC区域和源极/漏极区域，使得SiC区域包括与源极/漏极区域重叠的第一部分和从源极/漏极区域突出到LDD区域下方的位置的第二部分。 第二部分中结晶SiC的浓度高于第一部分中结晶SiC的浓度。 可以在形成第二间隔物之前通过正常注入形成SiC区域，或者可以在形成第二间隔物之后，通过在具有像σ形状的侧壁的凹槽中外延地倾斜注入或沉积来形成SiC区域。

    Method for fabricating metal-oxide semiconductor transistors
    4.
    发明授权
    Method for fabricating metal-oxide semiconductor transistors 有权
    金属氧化物半导体晶体管的制造方法

    公开(公告)号：US08053847B2

    公开(公告)日：2011-11-08

    申请号：US12324896

    申请日：2008-11-28

    Applicant: Tsai-Fu Hsiao ,  Ching-I Li ,  Po-Yuan Chen ,  Chun-An Lin ,  Hsiang-Ying Wang ,  Chao-Chun Chen ,  Chin-Cheng Chien

    Inventor： Tsai-Fu Hsiao ,  Ching-I Li ,  Po-Yuan Chen ,  Chun-An Lin ,  Hsiang-Ying Wang ,  Chao-Chun Chen ,  Chin-Cheng Chien

    IPC: H01L21/02

    CPC classification number: H01L21/324 ,  H01L21/265 ,  H01L21/2652 ,  H01L29/6659

    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.

    Abstract translation: 公开了一种制造金属氧化物半导体晶体管的方法。 首先，提供其上具有栅极结构的半导体衬底，并且在栅极结构周围形成间隔物。 进行离子注入工艺以在分隔体的两侧将含有碳，硼和氢的分子簇注入到半导体衬底中，以形成掺杂区域。 分子簇的分子量优选大于100.此后，进行毫秒退火处理以激活掺杂区域内的分子簇。

    METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTORS
    6.
    发明申请
    METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTORS 有权
    制备金属氧化物半导体晶体管的方法

    公开(公告)号：US20070196990A1

    公开(公告)日：2007-08-23

    申请号：US11675091

    申请日：2007-02-15

    Applicant: Tsai-Fu Hsiao ,  Ching-I Li ,  Po-Yuan Chen ,  Chun-An Lin ,  Hsiang-Ying Wang ,  Chao-Chun Chen ,  Chin-Cheng Chien

    Inventor： Tsai-Fu Hsiao ,  Ching-I Li ,  Po-Yuan Chen ,  Chun-An Lin ,  Hsiang-Ying Wang ,  Chao-Chun Chen ,  Chin-Cheng Chien

    IPC: H01L21/336

    CPC classification number: H01L21/324 ,  H01L21/265 ,  H01L21/2652 ,  H01L29/6659

    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.

    Abstract translation: 公开了一种制造金属氧化物半导体晶体管的方法。 首先，提供其上具有栅极结构的半导体衬底，并且在栅极结构周围形成间隔物。 执行离子注入工艺以将包含硼的分子簇注入围绕间隔物的半导体衬底中，以形成源/漏区。 分子簇内各硼原子的重量比优选小于10％。 此后，执行毫秒退火处理以激活源极/漏极区域内的分子簇。

    METHODS FOR USING ISOTOPICALLY ENRICHED LEVELS OF DOPANT GAS COMPOSITIONS IN AN ION IMPLANTATION PROCESS
    7.
    发明申请
    METHODS FOR USING ISOTOPICALLY ENRICHED LEVELS OF DOPANT GAS COMPOSITIONS IN AN ION IMPLANTATION PROCESS 有权
    在离子植入过程中使用同位素浓度多种气体组合物的方法

    公开(公告)号：US20140322902A1

    公开(公告)日：2014-10-30

    申请号：US13869456

    申请日：2013-04-24

    Applicant: Ashwini K. Sinha ,  Ching I. Li

    Inventor： Ashwini K. Sinha ,  Ching I. Li

    IPC: H01L21/265 ,  H01J27/02

    CPC classification number: H01J27/02 ,  H01J37/302 ,  H01J37/3171 ,  H01J2237/006 ,  H01J2237/08 ,  H01L21/26506 ,  H01L21/2658

    Abstract: A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified levels.

    Abstract translation: 本文提供了一种使用富集和高度富集的掺杂气体的新方法，其消除了终端用户目前遇到的问题，即能够实现与离子注入这种掺杂气体相关的工艺优点。 对于规定范围内的给定流速，在离子源的总功率水平降低的情况下操作，以减少富集的掺杂气体与其相应的非富集或较小浓度的掺杂气体相比的离子化效率。 源极丝的温度也降低，从而在使用富含氟的掺杂气体时减轻氟蚀刻和离子源短路的不利影响。 总功率的降低水平与较低的离子化效率和较低的离子源温度相结合可以相互协调地相互作用，以改善和延长离子源寿命，同时有利地保持不能接受地偏离先前合格水平的束流。

Patent Agency Ranking