公开(公告)号：US08383480B1

公开(公告)日：2013-02-26

申请号：US13295191

申请日：2011-11-14

Applicant: Chih-Ming Wang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin

Inventor： Chih-Ming Wang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin

IPC: H01L21/336

CPC classification number: H01L29/4234 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: A method for forming a semiconductor structure includes following steps. A substrate structure is provided. The substrate structure includes a semiconductor substrate, a first oxide-nitride-oxide (ONO) layer, and a second ONO layer. The semiconductor substrate has first and second surfaces opposite to each other. The first ONO layer includes a first oxide layer, a first nitride layer and a second oxide layer formed on the first surface in sequence. The second ONO layer includes a third oxide layer, a second nitride layer and a fourth oxide layer formed on the second surface in sequence. A nitride mask layer is formed on the first ONO layer. The fourth oxide layer is removed. The second nitride layer and the nitride mask layer are removed. The second oxide layer and the third oxide layer are removed. A fifth oxide layer is formed on the first nitride layer.

Abstract translation: 一种形成半导体结构的方法包括以下步骤。 提供了基板结构。 衬底结构包括半导体衬底，第一氧化物 - 氧化物 - 氧化物（ONO）层和第二ONO层。 半导体衬底具有彼此相对的第一和第二表面。 第一ONO层包括顺序地形成在第一表面上的第一氧化物层，第一氮化物层和第二氧化物层。 第二ONO层包括依次形成在第二表面上的第三氧化物层，第二氮化物层和第四氧化物层。 在第一ONO层上形成氮化物掩模层。 去除第四氧化物层。 去除第二氮化物层和氮化物掩模层。 去除第二氧化物层和第三氧化物层。 在第一氮化物层上形成第五氧化物层。

公开(公告)号：US20130026557A1

公开(公告)日：2013-01-31

申请号：US13189632

申请日：2011-07-25

Applicant: Chih-Ming WANG ,  Ping-Chia SHIH ,  Chun-Sung HUANG ,  Chi-Cheng HUANG ,  Hsiang-Chen LEE ,  Chih-Hung LIN ,  Yau-Kae SHEU

Inventor： Chih-Ming WANG ,  Ping-Chia SHIH ,  Chun-Sung HUANG ,  Chi-Cheng HUANG ,  Hsiang-Chen LEE ,  Chih-Hung LIN ,  Yau-Kae SHEU

IPC: H01L21/336 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L29/792

Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.

Abstract translation: 一种用于制造氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）非易失性存储单元的方法，其中该方法包括以下步骤：在衬底上依次形成衬垫氧化物层和第一硬掩模层。 然后将衬垫氧化物层和第一硬掩模层蚀刻通过以形成露出衬底的一部分的开口。 随后，形成具有基本上小于或等于该开口的尺寸的氧化物 - 氧化物 - 氧化物（ONO）结构，以与从该开口露出的该基板的一部分重合。

公开(公告)号：US20090218393A1

公开(公告)日：2009-09-03

申请号：US12347636

申请日：2008-12-31

Applicant: Chi-Cheng HUANG ,  Wei-Tse Cheng

Inventor： Chi-Cheng HUANG ,  Wei-Tse Cheng

IPC: G06F19/00

CPC classification number: G06K7/0008

Abstract: A method for disposing an RFID tag and a system thereof are provided. The RFID tag is disposed on a revolving region of an object. When the object rolls on a transporting platform, the object revolves around the revolving region. Therefore, an RFID reader reads a signal data transmitted from the RFID tag on the revolving region. In addition, the method can also be applied to a model that an object wraps a revolving axis of a transporting platform, and an RFID tag is disposed on a revolving region of the revolving axis of the transporting platform. When the revolving axis of the transporting platform rotates, an RFID reader can read correctly a signal data transmitted by the RFID tag on the revolving region of the revolving axis.

Abstract translation: 提供了一种用于设置RFID标签的方法及其系统。 RFID标签设置在物体的旋转区域上。 当物体在传送平台上滚动时，物体围绕旋转区域旋转。 因此，RFID读取器读取从旋转区域上的RFID标签发送的信号数据。 此外，该方法还可以应用于物体包裹传送平台的旋转轴的模型，并且RFID标签设置在传送平台的旋转轴的旋转区域上。 当传送平台的旋转轴旋转时，RFID读取器可以正确地读取由RFID标签在旋转轴的旋转区域上发送的信号数据。

公开(公告)号：US20100200905A1

公开(公告)日：2010-08-12

申请号：US12368223

申请日：2009-02-09

Applicant: Chun-Sung Huang ,  Ping-Chia Shih ,  Chiao-Lin Yang ,  Chi-Cheng Huang

Inventor： Chun-Sung Huang ,  Ping-Chia Shih ,  Chiao-Lin Yang ,  Chi-Cheng Huang

IPC: H01L29/51 ,  H01L21/336 ,  H01L21/302

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/66833

Abstract: A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.

Abstract translation: 一种用于制造NAND存储器单元的方法包括提供其中形成有第一掺杂区的衬底; 在基板上依次形成第一介电层，存储层和图案化的硬掩模; 通过图案化的硬掩模形成在衬底中限定多个凹槽的STI; 顺序地形成第二电介质层和填充衬底上的凹部的第一导电层; 以及执行平坦化处理以去除所述第一导电层和所述第二介电层的一部分以形成多个自对准岛状栅极结构。

公开(公告)号：US08546871B2

公开(公告)日：2013-10-01

申请号：US13177520

申请日：2011-07-06

Applicant: Chi-Cheng Huang ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chun-Sung Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

Inventor： Chi-Cheng Huang ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chun-Sung Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

IPC: H01L29/792

CPC classification number: H01L29/7923 ,  H01L29/66833

Abstract: A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.

Abstract translation: 非易失性存储单元包括衬底，两个电荷俘获结构，栅极氧化层，栅极和两个掺杂区域。 电荷捕获结构分别设置在基板上。 栅极氧化层设置在两个电荷俘获结构之间的衬底上。 栅极设置在栅极氧化物层和电荷捕获结构上，其中电荷捕获结构从栅极的两侧突出。 掺杂区域设置在栅极两侧的衬底中。

公开(公告)号：US20130234252A1

公开(公告)日：2013-09-12

申请号：US13412714

申请日：2012-03-06

Applicant: Hsiang-Chen LEE ,  Ping-Chia Shih ,  Ke-Chi Chen ,  Chih-Ming Wang ,  Chi-Cheng Huang

Inventor： Hsiang-Chen LEE ,  Ping-Chia Shih ,  Ke-Chi Chen ,  Chih-Ming Wang ,  Chi-Cheng Huang

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L21/82345 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857

Abstract: An integrated circuit includes a substrate, a first semiconductor device, a second semiconductor device and an interlayer dielectric layer. At least one isolation structure has been formed in the he substrate so as to separate the substrate into a first active region and a second active region. The first semiconductor device disposed on the first active region of the substrate includes a first gate insulating layer and a poly-silicon gate stacked on the substrate sequentially. The second semiconductor device disposed on the second active region of the substrate includes a second gate insulating layer and a metal gate stacked on the substrate sequentially. The material of the second gate insulating layer is different from that of the first gate insulating layer. The thickness of the metal gate is greater than that of the poly-silicon gate. The interlayer dielectric layer is disposed on the substrate and covering the first semiconductor device.

Abstract translation: 集成电路包括衬底，第一半导体器件，第二半导体器件和层间电介质层。 在衬底中形成至少一个隔离结构，以将衬底分离成第一有源区和第二有源区。 设置在基板的第一有源区上的第一半导体器件包括依次层叠在基板上的第一栅极绝缘层和多晶硅栅极。 设置在基板的第二有源区上的第二半导体器件包括依次层叠在基板上的第二栅极绝缘层和金属栅极。 第二栅极绝缘层的材料与第一栅极绝缘层的材料不同。 金属栅极的厚度大于多晶硅栅极的厚度。 层间介质层设置在基板上并覆盖第一半导体器件。

公开(公告)号：US20130009232A1

公开(公告)日：2013-01-10

申请号：US13177520

申请日：2011-07-06

Applicant: Chi-Cheng Huang ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chun-Sung Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

Inventor： Chi-Cheng Huang ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chun-Sung Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/7923 ,  H01L29/66833

Abstract: A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.

Abstract translation: 非易失性存储单元包括衬底，两个电荷俘获结构，栅极氧化层，栅极和两个掺杂区域。 电荷捕获结构分别设置在基板上。 栅极氧化层设置在两个电荷俘获结构之间的衬底上。 栅极设置在栅极氧化物层和电荷捕获结构上，其中电荷捕获结构从栅极的两侧突出。 掺杂区域设置在栅极两侧的衬底中。

公开(公告)号：US07973353B2

公开(公告)日：2011-07-05

申请号：US12368223

申请日：2009-02-09

Applicant: Chun-Sung Huang ,  Ping-Chia Shih ,  Chiao-Lin Yang ,  Chi-Cheng Huang

Inventor： Chun-Sung Huang ,  Ping-Chia Shih ,  Chiao-Lin Yang ,  Chi-Cheng Huang

IPC: H01L29/76 ,  H01L29/792 ,  H01L29/00

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/66833

Abstract: A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.

Abstract translation: 一种用于制造NAND存储器单元的方法包括提供其中形成有第一掺杂区的衬底; 在基板上依次形成第一介电层，存储层和图案化的硬掩模; 通过图案化的硬掩模形成在衬底中限定多个凹槽的STI; 顺序地形成第二电介质层和填充衬底上的凹部的第一导电层; 以及执行平坦化处理以去除所述第一导电层和所述第二介电层的一部分以形成多个自对准岛状栅极结构。

公开(公告)号：US07884774B2

公开(公告)日：2011-02-08

申请号：US11945711

申请日：2007-11-27

Applicant: Chi-Cheng Huang ,  Chia-Bin Yang

Inventor： Chi-Cheng Huang ,  Chia-Bin Yang

IPC: H01Q9/28

CPC classification number: H01Q9/42 ,  H01Q1/243 ,  H01Q9/0414 ,  H01Q9/0421 ,  H01Q21/28

Abstract: The present invention provides a wireless transmit/receive unit, comprising a feeding connecting line, a first radiating line, a second radiating line, a third radiating line and a fourth radiating line, wherein the third radiating line is longer than the first radiating line and the first radiating line is longer than the second radiating line that provides different current paths for getting a broader bandwidth. The first, second and third radiating lines are connected parallel for enhancing an antenna pattern being perpendicular thereto, and form a series capacity between the first and the third radiating lines. The fourth radiating line vertically connects between the third radiating line and a grounding line for forming a grounding capacity. The printed antenna can be reduced in size by the effect of the two capacities. The wireless transmit/receive unit can provide a better isolation with others by the direction enforced pattern and the reduced size.

Abstract translation: 本发明提供了一种无线发射/接收单元，包括馈电连接线，第一辐射线，第二辐射线，第三辐射线和第四辐射线，其中第三辐射线比第一辐射线长， 第一辐射线比提供用于获得更宽带宽的不同电流路径的第二辐射线更长。 第一，第二和第三辐射线并联连接以增强与其垂直的天线图案，并且在第一和第三辐射线之间形成串联容量。 第四辐射线在第三辐射线和用于形成接地能力的接地线之间垂直连接。 印刷天线可以通过两种容量的作用而减小尺寸。 无线发射/接收单元可以通过方向强制模式和减小的尺寸与其他方式提供更好的隔离。

公开(公告)号：US08629025B2

公开(公告)日：2014-01-14

申请号：US13403591

申请日：2012-02-23

Applicant: Ko-Chi Chen ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee

Inventor： Ko-Chi Chen ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.

Abstract translation: 对半导体装置的制造方法进行说明。 堆叠的栅极电介质形成在衬底上，包括从底部到顶部的第一介电层，第二电介质层和第三电介质层。 在堆叠的栅极电介质上形成导电层，然后将其图案化以形成栅极导体。 通过选择性湿式清洗步骤除去第三和第二介电层的暴露部分。 在栅极导体作为掩模的基板中形成S / D延伸区域。 在栅极导体的侧壁上形成第一间隔物，并且去除由第一间隔物露出的第一电介质层的一部分。 在第一间隔物的两侧的基板中形成S / D区域。 在S / D区域上形成金属硅化物层。