公开(公告)号：US08722488B2

公开(公告)日：2014-05-13

申请号：US13451565

申请日：2012-04-20

Applicant: Ping-Chia Shih

Inventor： Ping-Chia Shih

IPC: H01L21/336

CPC classification number: H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

Abstract: A method of fabricating a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, and a material layer covering the gate stack layers is formed on the semiconductor substrate. Subsequently, a part of the material layer is removed to form a sacrificial layer between the gate stack layers, and a spacer at the opposite lateral sides of the gate stack layers. Furthermore, a patterned mask covering the gate stack layers and the spacer and exposing the sacrificial layer is formed, and the sacrificial layer is removed.

Abstract translation: 制造半导体器件的方法包括以下步骤。 首先，在半导体衬底上形成两个栅堆叠层，并且在半导体衬底上形成覆盖栅堆叠层的材料层。 随后，去除材料层的一部分以在栅极叠层之间形成牺牲层，以及栅极叠层层的相对侧面处的间隔物。 此外，形成覆盖栅堆叠层和间隔物并暴露牺牲层的图案化掩模，并且去除牺牲层。

公开(公告)号：US08633079B2

公开(公告)日：2014-01-21

申请号：US12690924

申请日：2010-01-20

Applicant: Ping-Chia Shih ,  Yu-Cheng Yin

Inventor： Ping-Chia Shih ,  Yu-Cheng Yin

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L27/11573

Abstract: A method for fabricating SONOS memory is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer on the surface of the semiconductor substrate; forming a hard mask on the second silicon oxide layer; patterning the hard mask, the second silicon oxide layer, the silicon nitride layer, and the first silicon oxide layer to form a patterned hard mask and a stacked structure; forming a gate oxide layer on surface of the patterned hard mask; removing the gate oxide layer and the patterned hard mask; forming a patterned polysilicon layer on surface of the stacked structure; and forming a source/drain region in the semiconductor substrate adjacent to two sides of the polysilicon layer.

Abstract translation: 公开了一种用于制造SONOS存储器的方法。 该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底的表面上形成第一氧化硅层，氮化硅层和第二氧化硅层; 在所述第二氧化硅层上形成硬掩模; 图案化硬掩模，第二氧化硅层，氮化硅层和第一氧化硅层，以形成图案化的硬掩模和堆叠结构; 在所述图案化硬掩模的表面上形成栅氧化层; 去除栅极氧化物层和图案化的硬掩模; 在所述堆叠结构的表面上形成图案化的多晶硅层; 以及在与所述多晶硅层的两侧相邻的所述半导体衬底中形成源极/漏极区域。

公开(公告)号：US08629025B2

公开(公告)日：2014-01-14

申请号：US13403591

申请日：2012-02-23

Applicant: Ko-Chi Chen ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee

Inventor： Ko-Chi Chen ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.

Abstract translation: 对半导体装置的制造方法进行说明。 堆叠的栅极电介质形成在衬底上，包括从底部到顶部的第一介电层，第二电介质层和第三电介质层。 在堆叠的栅极电介质上形成导电层，然后将其图案化以形成栅极导体。 通过选择性湿式清洗步骤除去第三和第二介电层的暴露部分。 在栅极导体作为掩模的基板中形成S / D延伸区域。 在栅极导体的侧壁上形成第一间隔物，并且去除由第一间隔物露出的第一电介质层的一部分。 在第一间隔物的两侧的基板中形成S / D区域。 在S / D区域上形成金属硅化物层。

公开(公告)号：US20130307049A1

公开(公告)日：2013-11-21

申请号：US13472499

申请日：2012-05-16

Applicant: Ping-Chia Shih

Inventor： Ping-Chia Shih

IPC: H01L29/788 ,  H01L21/283

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A method of fabricating a semiconductor device includes the following steps. At first, a semiconductor substrate is provided. A gate stack layer is formed on the semiconductor substrate, and the gate stack layer further includes a cap layer disposed thereon. Furthermore, two first spacers surrounding sidewalls of the gate stack layer is further formed. Subsequently, the cap layer is removed, and two second spacers are formed on a part of the gate stack layer. Afterwards, a part of the first spacers and the gate stack layer not overlapped with the two second spacers are removed to form two gate stack structures.

Abstract translation: 制造半导体器件的方法包括以下步骤。 首先，提供半导体衬底。 在半导体衬底上形成栅堆叠层，并且栅层叠层还包括设置在其上的盖层。 此外，进一步形成围绕栅堆叠层的侧壁的两个第一间隔物。 随后，除去盖层，并且在栅极堆叠层的一部分上形成两个第二间隔物。 之后，除去不与两个第二间隔物重叠的第一间隔物和栅极堆叠层的一部分以形成两个栅叠层结构。

公开(公告)号：US20130221424A1

公开(公告)日：2013-08-29

申请号：US13403591

申请日：2012-02-23

Applicant: Ko-Chi Chen ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee

Inventor： Ko-Chi Chen ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.

Abstract translation: 对半导体装置的制造方法进行说明。 堆叠的栅极电介质形成在衬底上，包括从底部到顶部的第一介电层，第二电介质层和第三电介质层。 在堆叠的栅极电介质上形成导电层，然后将其图案化以形成栅极导体。 通过选择性湿式清洗步骤除去第三和第二介电层的暴露部分。 在栅极导体作为掩模的基板中形成S / D延伸区域。 在栅极导体的侧壁上形成第一间隔物，并且去除由第一间隔物露出的第一电介质层的一部分。 在第一间隔物的两侧的基板中形成S / D区域。 在S / D区域上形成金属硅化物层。

公开(公告)号：US08119489B2

公开(公告)日：2012-02-21

申请号：US12058183

申请日：2008-03-28

Applicant: Ping-Chia Shih

Inventor： Ping-Chia Shih

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/302 ,  H01L21/31 ,  H01L21/3205

CPC classification number: H01L21/76224 ,  H01L27/1052

Abstract: A method of fabricating an isolation structure and the structure thereof is provided. The method is compatible with the embedded memory process and provides the isolation structure with a poly cap thereon to protect the top corners of the isolation structure, without using an extra photomask.

Abstract translation: 提供了制造隔离结构的方法及其结构。 该方法与嵌入式存储器处理兼容，并且在隔离结构上提供具有多个盖的隔离结构，以保护隔离结构的顶角，而不使用额外的光掩模。

公开(公告)号：US08034690B2

公开(公告)日：2011-10-11

申请号：US12696055

申请日：2010-01-29

Applicant: Ping-Chia Shih ,  Yu-Cheng Wang ,  Chun-Sung Huang ,  Yuan-Cheng Yang ,  Chung-Che Huang ,  Chin-Fu Lin

Inventor： Ping-Chia Shih ,  Yu-Cheng Wang ,  Chun-Sung Huang ,  Yuan-Cheng Yang ,  Chung-Che Huang ,  Chin-Fu Lin

IPC: H01L21/336

CPC classification number: H01L21/311

Abstract: An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.

Abstract translation: 提供蚀刻氧化物层和氮化物层的示例性方法。 特别地，提供了基板。 基板的表面具有从其突出的隔离结构。 第一氧化物层，氮化物层和第二氧化物层依次设置在衬底的表面上，其中第一氧化物层未被覆盖在隔离结构上，氮化物层形成在第一氧化物层上，第二氧化物 层叠在氮化物层上。 通过使用非掩蔽隔离结构的蚀刻掩模进行各向同性蚀刻处理，从而去除第二氧化物层的未掩模部分和氮化物层的未掩模部分，并进一步暴露隔离结构的侧壁。 由于过蚀刻，第一氧化物层的未掩模部分通常被部分去除。

公开(公告)号：US20110189859A1

公开(公告)日：2011-08-04

申请号：US12696055

申请日：2010-01-29

Applicant: Ping-Chia Shih ,  Yu-Cheng Wang ,  Chun-Sung Huang ,  Yuan-Cheng Yang ,  Chung-Che Huang ,  Chin-Fu Lin

Inventor： Ping-Chia Shih ,  Yu-Cheng Wang ,  Chun-Sung Huang ,  Yuan-Cheng Yang ,  Chung-Che Huang ,  Chin-Fu Lin

IPC: H01L21/311

CPC classification number: H01L21/311

Abstract: An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.

Abstract translation: 提供蚀刻氧化物层和氮化物层的示例性方法。 特别地，提供了基板。 基板的表面具有从其突出的隔离结构。 第一氧化物层，氮化物层和第二氧化物层依次设置在衬底的表面上，其中第一氧化物层未被覆盖在隔离结构上，氮化物层形成在第一氧化物层上，第二氧化物 层叠在氮化物层上。 通过使用非掩蔽隔离结构的蚀刻掩模进行各向同性蚀刻处理，从而去除第二氧化物层的未掩模部分和氮化物层的未掩模部分，并进一步暴露隔离结构的侧壁。 由于过蚀刻，第一氧化物层的未掩模部分通常被部分去除。

公开(公告)号：US20110177664A1

公开(公告)日：2011-07-21

申请号：US12690924

申请日：2010-01-20

Applicant: Ping-Chia Shih ,  Yu-Cheng Yin

Inventor： Ping-Chia Shih ,  Yu-Cheng Yin

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L27/11573

Abstract: A method for fabricating SONOS memory is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer on the surface of the semiconductor substrate; forming a hard mask on the second silicon oxide layer; patterning the hard mask, the second silicon oxide layer, the silicon nitride layer, and the first silicon oxide layer to form a patterned hard mask and a stacked structure; forming a gate oxide layer on surface of the patterned hard mask; removing the gate oxide layer and the patterned hard mask; forming a patterned polysilicon layer on surface of the stacked structure; and forming a source/drain region in the semiconductor substrate adjacent to two sides of the polysilicon layer.

Abstract translation: 公开了一种制造SONOS存储器的方法。 该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底的表面上形成第一氧化硅层，氮化硅层和第二氧化硅层; 在所述第二氧化硅层上形成硬掩模; 图案化硬掩模，第二氧化硅层，氮化硅层和第一氧化硅层以形成图案化的硬掩模和堆叠结构; 在所述图案化硬掩模的表面上形成栅氧化层; 去除栅极氧化物层和图案化的硬掩模; 在所述堆叠结构的表面上形成图案化的多晶硅层; 以及在与所述多晶硅层的两侧相邻的所述半导体衬底中形成源极/漏极区域。

公开(公告)号：US20110044109A1

公开(公告)日：2011-02-24

申请号：US12542711

申请日：2009-08-18

Applicant: Ping-Chia Shih ,  Chung-Chin Shih

Inventor： Ping-Chia Shih ,  Chung-Chin Shih

IPC: G11C14/00 ,  G11C5/14

CPC classification number: G11C14/0063

Abstract: A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.

Abstract translation: 非易失性静态随机存取存储器（NVSRAM）装置包括易失性电路和非易失性电路。 在提供外部电源的正常操作下，易失性电路可以提供快速的数据访问。 当电源以某种方式中断时，非易失性电路可以使用逆变器电路和非易失性可擦除可编程存储器（NVEPM）电路提供数据备份，从而保留先前存储在易失性电路中的数据。