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    Heat dissipation package structure and method for fabricating the same
    1.
    发明授权
    Heat dissipation package structure and method for fabricating the same 有权
    散热封装结构及其制造方法

    公开(公告)号：US08013436B2

    公开(公告)日：2011-09-06

    申请号：US12157831

    申请日：2008-06-13

    Applicant: Min-Shun Hung ,  Yo-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

    Inventor： Min-Shun Hung ,  Yo-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

    IPC: H01L23/34

    CPC classification number: H01L23/4334 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2224/0401 ,  H01L2224/45099

    Abstract: A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant. Therefore, the heat dissipation package structure is fabricated through simplified fabrication steps at low cost, and also the problem that the chip is easily damaged in a package molding process of the prior art is overcome.

    Abstract translation: 公开了一种散热封装结构及其制造方法，其包括通过其有源表面安装和电连接半导体芯片到芯片载体; 将具有散热部和支撑部的散热部件安装在所述芯片载体上，使得所述半导体芯片能够容纳在由所述散热部和所述支撑部形成的空间中，其中，所述散热部具有相应形成的开口 到半导体芯片; 形成密封剂以封装半导体芯片和散热构件; 并且使所述密封剂变薄以除去形成在所述半导体芯片上的所述密封剂，以从所述密封剂暴露所述半导体芯片的无效表面和所述散热部分的顶表面。 因此，通过以低成本的简化的制造步骤制造散热封装结构，并且克服了在现有技术的封装成型工艺中芯片容易损坏的问题。

    Stack structure of semiconductor packages and method for fabricating the stack structure
    2.
    发明授权
    Stack structure of semiconductor packages and method for fabricating the stack structure 有权
    半导体封装的堆叠结构和制造堆叠结构的方法

    公开(公告)号：US07855443B2

    公开(公告)日：2010-12-21

    申请号：US11732853

    申请日：2007-04-04

    Applicant: Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

    Inventor： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

    IPC: H01L23/02

    CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

    Abstract translation: 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。

    Heat dissipation semiconductor package
    4.
    发明授权
    Heat dissipation semiconductor package 有权
    散热半导体封装

    公开(公告)号：US07608915B2

    公开(公告)日：2009-10-27

    申请号：US12151902

    申请日：2008-05-08

    Applicant: Chun-Ming Liao ,  Chien-Ping Huang ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

    Inventor： Chun-Ming Liao ,  Chien-Ping Huang ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

    IPC: H01L23/495 ,  H01J23/10

    CPC classification number: H01L23/4334 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

    Abstract: A heat dissipation semiconductor package includes a chip carrier, a semiconductor chip, a heat conductive adhesive, a heat dissipation member, and an encapsulant. The semiconductor chip is flip-chip mounted on the chip carrier and defined with a heat conductive adhesive mounting area. Periphery of the heat adhesive mounting area is spaced apart from edge of the semiconductor chip. The heat dissipation member is mounted on the heat conductive adhesive formed in the heat conductive adhesive mounting area. The encapsulant formed between the chip carrier and the heat dissipation member encapsulates the semiconductor chip and the heat conductive adhesive, and embeds edges of the active surface and non-active surface and side edge of the semiconductor chip, thereby increasing bonding area between the encapsulant and the semiconductor chip. The side edges of the heat conductive adhesive and the semiconductor chip are not flush with each other, thereby preventing propagation of delamination.

    Abstract translation: 散热半导体封装包括芯片载体，半导体芯片，导热粘合剂，散热构件和密封剂。 半导体芯片倒装芯片安装在芯片载体上，并用导热粘合剂安装区域限定。 热粘合剂安装区域的周边与半导体芯片的边缘间隔开。 散热构件安装在形成在导热粘合剂安装区域中的导热粘合剂上。 形成在芯片载体和散热构件之间的密封剂封装半导体芯片和导热粘合剂，并且嵌入半导体芯片的有源表面和非有源表面和侧边缘的边缘，从而增加密封剂和 半导体芯片。 导热粘合剂和半导体芯片的侧边缘彼此不齐平，从而防止分层的蔓延。

    Semiconductor package and method for fabricating the same
    6.
    发明申请
    Semiconductor package and method for fabricating the same 审中-公开
    半导体封装及其制造方法

    公开(公告)号：US20090102063A1

    公开(公告)日：2009-04-23

    申请号：US12287936

    申请日：2008-10-14

    Applicant: Chun-Yuan Lee ,  Chien Ping Huang ,  Yu-Ting Lai ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

    Inventor： Chun-Yuan Lee ,  Chien Ping Huang ,  Yu-Ting Lai ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

    IPC: H01L23/48 ,  H01L21/00

    CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: This invention provides a semiconductor package and a method for fabricating the same. The method includes: forming a first resist layer on a metal carrier; forming a plurality of openings penetrating the first resist layer; forming a conductive metal layer in the openings; removing the first resist layer; covering the metal carrier having the conductive metal layer with a dielectric layer; forming blind vias in the dielectric layer to expose a portion of the conductive metal layer; forming conductive circuit on the dielectric layer and conductive posts in the blind vias, such that the conductive circuit is electrically connected to the conductive metal layer via the conductive posts; electrically connecting at least one chip to the conductive circuit; forming an encapsulant for encapsulating the chip and the conductive circuit; and removing the metal carrier, thereby allowing a semiconductor package to be formed without a chip carrier. Given the conductive posts, both the conductive circuit and conductive metal layer are efficiently coupled to the dielectric layer to prevent delamination. Further, downsizing the blind vias facilitates the fabrication process and cuts the fabrication cost.

    Abstract translation: 本发明提供一种半导体封装及其制造方法。 该方法包括：在金属载体上形成第一抗蚀剂层; 形成穿过所述第一抗蚀剂层的多个开口; 在所述开口中形成导电金属层; 去除第一抗蚀剂层; 用介电层覆盖具有导电金属层的金属载体; 在介电层中形成盲孔以暴露导电金属层的一部分; 在介电层上形成导电电路和在盲孔中的导电柱，使得导电电路经由导电柱电连接到导电金属层; 将至少一个芯片电连接到所述导电电路; 形成用于封装所述芯片和所述导电电路的密封剂; 并且去除金属载体，从而允许在没有芯片载体的情况下形成半导体封装。 给定导电柱，导电电路和导电金属层都有效地耦合到电介质层以防止分层。 此外，缩小盲孔通孔有助于制造工艺并降低制造成本。

    Sensor package and method for fabricating the same
    7.
    发明申请
    Sensor package and method for fabricating the same 审中-公开
    传感器封装及其制造方法

    公开(公告)号：US20080303111A1

    公开(公告)日：2008-12-11

    申请号：US12156901

    申请日：2008-06-05

    Applicant: Chang-Yueh Chan ,  Chien-Ping Huang ,  Tse-Wen Chang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    Inventor： Chang-Yueh Chan ,  Chien-Ping Huang ,  Tse-Wen Chang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    IPC: H01L31/0203 ,  H01L31/18

    CPC classification number: H01L31/0203 ,  H01L23/24 ,  H01L31/18 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: The invention discloses a sensor package and a method for fabricating the same. The sensor package includes: a substrate with an opening; a sensor chip disposed in the opening and electrically connected to the substrate; an encapsulant filling spacing between the sensor chip and the opening so as to secure the sensor chip to the substrate; and a transparent cover attached to the substrate via an adhesive layer, wherein the adhesive layer covers the sensor chip and bonding wires and is formed with an opening for exposing sensor region of the sensor chip. Securing the sensor chip in the opening of the substrate reduces the height of the sensor package, and meanwhile the process cost is reduced by eliminating the need of formation of conductive bumps on the sensor chip or the transparent cover and eliminating the need of specially designed substrate.

    Abstract translation: 本发明公开了一种传感器封装及其制造方法。 传感器封装包括：具有开口的基板; 传感器芯片，其布置在所述开口中并电连接到所述基板; 传感器芯片和开口之间的密封剂填充间隔，以将传感器芯片固定到基板上; 以及通过粘合剂层附着到基板的透明盖，其中粘合剂层覆盖传感器芯片和接合线，并且形成有用于暴露传感器芯片的传感器区域的开口。 将传感器芯片固定在基板的开口中，降低传感器封装的高度，同时通过消除在传感器芯片或透明盖上形成导电凸块的需要降低工艺成本，并且不需要特别设计的基板 。

    Stackable semiconductor device and manufacturing method thereof
    10.
    发明申请
    Stackable semiconductor device and manufacturing method thereof 审中-公开
    可堆叠半导体器件及其制造方法

    公开(公告)号：US20080251937A1

    公开(公告)日：2008-10-16

    申请号：US12082724

    申请日：2008-04-11

    Applicant: Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    Inventor： Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

    IPC: H01L23/52 ,  H01L21/00

    CPC classification number: H01L21/76898 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/00014

    Abstract: A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of any two adjacent ones of the chips; forming a dielectric layer on regions between the solder pads of any two adjacent ones of the chips ; forming a metal layer on the dielectric layer electrically connected to the solder pads and forming a connective layer on the metal layer, wherein the width of the connective layer is smaller than that of the metal layer; cutting along the grooves to break off the electrical connection between adjacent chips; thinning the non-active surface of the wafer to the extent that the metal layer is exposed from the wafer; and separating the chips to form a plurality of stackable semiconductor devices. Accordingly, a multi-chip stack structure can be obtained by stacking and electrically connecting a plurality of semiconductor devices through the electrical connection between the connective layer of a semiconductor device and the metal layer of another semiconductor device, thereby effectively integrating more chips without having to increase the stacking area, and further the problems of poor electrical connection, complicated manufacturing processes and high costs known in the prior art can be avoided.

    Abstract translation: 公开了一种可堆叠半导体器件及其制造方法。 该方法包括提供由多个芯片组成的晶片，其中在每个芯片的有源表面上形成多个焊盘，并且在任何两个相邻芯片的焊盘之间形成多个沟槽; 在任何两个相邻芯片的焊盘之间的区域上形成电介质层; 在与所述焊料焊盘电连接的所述电介质层上形成金属层，并在所述金属层上形成连接层，其中所述连接层的宽度小于所述金属层的宽度; 沿着凹槽切割以破坏相邻芯片之间的电连接; 使晶片的非活性表面变薄至金属层从晶片露出的程度; 并分离所述芯片以形成多个可堆叠半导体器件。 因此，通过半导体器件的连接层与另一半导体器件的金属层之间的电连接层叠并电连接多个半导体器件，可以获得多芯片堆叠结构，从而有效地集成更多的芯片，而不必 增加堆积面积，进一步避免了现有技术中已知的电连接不良，制造工艺复杂，成本高的问题。

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