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    Nonvolatile memory device using variable resistive element
    1.
    发明授权
    Nonvolatile memory device using variable resistive element 有权
    使用可变电阻元件的非易失性存储器件

    公开(公告)号：US08264905B2

    公开(公告)日：2012-09-11

    申请号：US12406441

    申请日：2009-03-18

    申请人： Byung-Gil Choi ,  Du-Eung Kim

    发明人： Byung-Gil Choi ,  Du-Eung Kim

    IPC分类号： G11C16/08

    CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2029/1202

    摘要： A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls voltage level of the multiple sub-word lines, wherein the section word line driver includes multiple pull-down elements which are connected to each of the multiple sub-word lines and a common node and a selection element which is connected to the common node and the main word line.

    摘要翻译： 提供了使用可变电阻元件的非易失性存储器件，其具有减小的布局尺寸和改进的性能。 所述非易失性存储器件包括：主字线; 多个子字线，其中每个子字线连接到多个非易失性存储器单元; 以及区域字线驱动器，其控制所述多个子字线的电压电平，其中所述部分字线驱动器包括连接到所述多个子字线中的每一个的多个下拉元件，以及公共节点和选择元件 其连接到公共节点和主字线。

    Nonvolatile memory device and method of driving the same
    2.
    发明授权
    Nonvolatile memory device and method of driving the same 有权
    非易失存储器件及其驱动方法

    公开(公告)号：US08085575B2

    公开(公告)日：2011-12-27

    申请号：US12585728

    申请日：2009-09-23

    申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Hye-Jin Kim

    发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Hye-Jin Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0023 ,  G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026

    摘要： A nonvolatile memory device and a method of driving the same are provided, which adopt an improved write operation. The method of driving a nonvolatile memory device includes providing the nonvolatile memory device including a plurality of memory banks each having a plurality of local bit lines and a plurality of variable resistance memory cells; selectively connecting read global bit lines for reading data with the local bit lines, and firstly discharging the selectively connected local bit lines by turning on local bit line discharge transistors coupled to the read global bit lines; and selectively connecting write global bit lines for writing data with the local bit lines, and secondly discharging the selectively connected local bit lines by turning on global bit line discharge transistors.

    摘要翻译： 提供一种非易失性存储器件及其驱动方法，其采用改进的写入操作。 驱动非易失性存储器件的方法包括提供包括多个存储体的非易失性存储器件，每个存储器组具有多个局部位线和多个可变电阻存储器单元; 选择性地连接读取全局位线用于与局部位线一起读取数据，并且首先通过连接耦合到读出的全局位线的局部位线放电晶体管来放电选择性连接的局部位线; 并选择性地连接用于将数据写入本地位线的写入全局位线，以及其次通过导通全局位线放电晶体管对选择连接的局部位线进行放电。

    Resistive memory devices using assymetrical bitline charging and discharging
    3.
    发明授权
    Resistive memory devices using assymetrical bitline charging and discharging 失效
    使用不对称位线充电和放电的电阻式存储器件

    公开(公告)号：US08027192B2

    公开(公告)日：2011-09-27

    申请号：US12544058

    申请日：2009-08-19

    申请人： Byung-Gil Choi

    发明人： Byung-Gil Choi

    IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C7/00 ,  G11C8/08

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C8/08 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

    摘要： A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.

    摘要翻译： 非易失性存储器件包括多个存储体，每个存储体包括多个非易失性电阻存储单元（例如PRAM单元）。 该设备还包括由存储体共享的写入全局位线和由存储体共享的读出的全局位线。 该装置还包括一个控制电路，该控制电路被配置为使用读写全局位线在第一存储体中使用读出的全局位线从第一存储器组中的选定的非易失存储单元读取数据，从而将数据写入第一存储器组中的选定非易失存储单元， 写入全局位线的时间段比流经第一存储体的非易失性存储单元的写入电流的淬灭时间长。

    Phase change memory
    4.
    发明授权
    Phase change memory 有权
    相变记忆

    公开(公告)号：US08023319B2

    公开(公告)日：2011-09-20

    申请号：US12457319

    申请日：2009-06-08

    申请人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

    发明人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

    IPC分类号： G11C11/00

    CPC分类号： G11C29/808 ,  G11C13/0004

    摘要： The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

    摘要翻译： 所述相变存储器件包括多个存储体，连接到所述多个存储体的多个局部导体线，连接到所述多个局部导体线的至少一个全局导体线，以及至少一个修理控制电路， 选择性地将所述至少一个全局导体线中的至少一个与至少一个冗余全局导体线替换并且被配置为用至少一个冗余局部导体线选择性地替换所述多条局部导体线中的至少一个。

    Variable resistance memory device and method of manufacturing the same
    7.
    发明授权
    Variable resistance memory device and method of manufacturing the same 有权
    可变电阻存储器件及其制造方法

    公开(公告)号：US07808815B2

    公开(公告)日：2010-10-05

    申请号：US11865491

    申请日：2007-10-01

    申请人： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

    发明人： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

    IPC分类号： G11C11/00

    CPC分类号： G11C5/063 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/24 ,  Y10S977/754

    摘要： A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

    摘要翻译： 一种可变电阻存储器件，包括衬底，形成在衬底上的多个有源线，被均匀地分离并沿着第一方向延伸，多个开关器件形成在有源线上并彼此分离，多个 分别形成在开关装置上并连接到开关装置的可变电阻装置，形成在可变电阻装置上的多个局部位线被均匀分离，在第二方向上延伸，并且连接到可变电阻装置，多个局部字 形成在局部位线上的线被均匀地分离，并且在第一方向上延伸，形成在局部字线上的多个全局位线被均匀分离，并且在第二方向上延伸，并且多个全局字线 形成在全局位线上，均匀分离，并沿第一方向延伸。

    PHASE-CHANGE RANDOM ACCESS MEMORY
    8.
    发明申请
    PHASE-CHANGE RANDOM ACCESS MEMORY 有权
    相变随机存取存储器

    公开(公告)号：US20100214832A1

    公开(公告)日：2010-08-26

    申请号：US12771028

    申请日：2010-04-30

    申请人： BYUNG-GIL CHOI ,  DU-EUNG KIM ,  WOO-YEONG CHO ,  HYE-JIN KIM

    发明人： BYUNG-GIL CHOI ,  DU-EUNG KIM ,  WOO-YEONG CHO ,  HYE-JIN KIM

    IPC分类号： G11C11/00 ,  G11C29/00

    CPC分类号： G11C29/808 ,  G11C29/02 ,  G11C29/027 ,  G11C29/787 ,  G11C29/804 ,  G11C29/846

    摘要： A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.

    摘要翻译： 相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量 控制信号。

    VARIABLE RESISTIVE MEMORY
    9.
    发明申请
    VARIABLE RESISTIVE MEMORY 有权
    可变电阻记忆

    公开(公告)号：US20100110771A1

    公开(公告)日：2010-05-06

    申请号：US12623659

    申请日：2009-11-23

    申请人： Byung-Gil Choi

    发明人： Byung-Gil Choi

    IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C8/08

    CPC分类号： G11C8/14 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/02

    摘要： A variable resistive memory device includes memory sectors, memory cells in each of the memory sectors, sub-wordlines including a first in signal communication with at least a first pair of the memory cells in a first sector and a second in signal communication with at least a second pair of the memory cells in a second sector, local bitlines where each is in signal communication a memory cell, a local bitline selecting signal generator in signal communication with local bitline selecting signal paths, a first local bitline selecting signal path in signal communication with a first pair of the local bitlines, and a second local bitline selecting signal path in signal communication with a second pair of the plurality of local bitlines, where a first of the first pair of local bitlines is in signal communication with a first of the first pair of the memory cells in the first sector and a second of the first pair of local bitlines is in signal communication with a second of the second pair of the memory cells in the second sector, and a first of the second pair of local bitlines is in signal communication with a second of the first pair of the memory cells in the first sector and a second of the second pair of local bitlines is in signal communication with a first of the second pair of the memory cells in the second sector.

    摘要翻译： 可变电阻存储器件包括存储器扇区，每个存储器扇区中的存储器单元，子字线包括与第一扇区中的至少第一对存储器单元的信号通信的第一信号，以及至少与第一扇区信号通信的第二信号 第二扇区中的第二对存储单元，其中每个存储单元在存储单元中进行信号通信的本地位线，与本地位线选择信号路径进行信号通信的本地位线选择信号发生器，信号通信中的第一本地位线选择信号路径 具有第一对本地位线，以及与第二对多个本地位线进行信号通信的第二本地位线选择信号路径，其中第一对本地位线中的第一对与第一对本地位线信号通信 第一扇区中的第一对存储单元和第一对本地位线中的第二对与第二列的第二对信号通信 第二扇区中的存储器单元的第一和第二对本地位线中的第一对与第一扇区中的第一对存储单元中的第二对应信号通信，并且第二对本地位线中的第二对是 与第二扇区中的第二对存储单元中的第一对信号通信。