公开(公告)号：US07619298B1

公开(公告)日：2009-11-17

申请号：US11095812

申请日：2005-03-31

Applicant: Firas N. Abughazaleh ,  Brian T. Brunn

Inventor： Firas N. Abughazaleh ,  Brian T. Brunn

IPC: H01L27/108

CPC classification number: H01L21/76 ,  H01L27/0629 ,  H01L27/0676 ,  H01L27/0805 ,  H01L28/40

Abstract: A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.

Abstract translation: 一种降低寄生电容的方法和装置。 P阱封闭层直接形成在寄生器件的正下方。 P阱阻挡层显着增加寄生器件下方的电阻。 实际上，P阱阻挡层的电阻实际上部分地将寄生器件与接地端子断开，以最小化添加到总终端阻抗的有效电容阻抗。

公开(公告)号：US07224760B1

公开(公告)日：2007-05-29

申请号：US10421512

申请日：2003-04-22

Applicant: Shahriar Rokhsaz ,  Moises E. Robinson ,  Ahmed Younis ,  Brian T. Brunn

Inventor： Shahriar Rokhsaz ,  Moises E. Robinson ,  Ahmed Younis ,  Brian T. Brunn

IPC: H03D3/24

CPC classification number: H04L7/0331 ,  H03D13/003 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/091 ,  H03L7/10

Abstract: A high-speed, wide bandwidth data detection circuit includes a phase detection module, a data detection module, a loop filter, and a voltage controlled oscillator. The phase detection module is operably coupled to produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock. The phase detection module performs the current mode mathematical manipulations and produces the controlled current in the current domain. The data detection module is operably coupled to produce the detected data based on the incoming data stream and the recovered clock. The loop filter is operably coupled to convert the controlled current into a controlled voltage. The voltage controlled oscillator is operably coupled to convert the control voltage into the recovered clock.

Abstract translation: 高速，宽带宽数据检测电路包括相位检测模块，数据检测模块，环路滤波器和压控振荡器。 相位检测模块可操作地耦合以基于对输入数据流和恢复的时钟之间的差异的当前模式数学操作产生受控电流。 相位检测模块执行当前模式的数学操作并产生当前域中的受控电流。 数据检测模块可操作地耦合以基于输入数据流和恢复的时钟产生检测到的数据。 环路滤波器可操作地耦合以将受控电流转换成受控电压。 压控振荡器可操作地耦合以将控制电压转换成恢复的时钟。

公开(公告)号：US07184466B1

公开(公告)日：2007-02-27

申请号：US10243411

申请日：2002-09-12

Applicant: Brian K. Seemann ,  Brian T. Brunn ,  Normand T. Lemay, Jr. ,  Daniel J. Ferris, III ,  Thomas Anthony Lee ,  James M. Simkins ,  David B. Squires

Inventor： Brian K. Seemann ,  Brian T. Brunn ,  Normand T. Lemay, Jr. ,  Daniel J. Ferris, III ,  Thomas Anthony Lee ,  James M. Simkins ,  David B. Squires

IPC: H04B1/38

CPC classification number: H04B1/406 ,  H04B1/0003

Abstract: A data conveyance integrated system that can be utilized in a base station and/or end user devices in a wireless communication system. The integrated system includes first and second integrated circuits (ICs). The first IC includes a first serial-deserial (SERDES) module, a transmit radio frequency module, and a receive radio frequency module. The transmit and receive radio frequency modules provide the wireless communication between the base stations and end user devices. The second IC includes a second SERDES module and a programmable logic fabric programmed to implement one or more wireless communication functions. Accordingly, the programmable logic fabric generates outbound digital signals from data (e.g., video, audio, control, or text data) provided to the device, and/or processes inbound digital signals to recapture the originally transmitted data. Thus, base stations and/or end user devices within a wireless communication system can be readily reconfigured.

Abstract translation: 一种可在无线通信系统中的基站和/或终端用户设备中使用的数据传输集成系统。 集成系统包括第一和第二集成电路（IC）。 第一IC包括第一串并联（SERDES）模块，发射射频模块和接收射频模块。 发射和接收射频模块提供基站和终端用户设备之间的无线通信。 第二IC包括被编程为实现一个或多个无线通信功能的第二SERDES模块和可编程逻辑结构。 因此，可编程逻辑结构从提供给设备的数据（例如，视频，音频，控制或文本数据）生成出站数字信号，和/或处理入站数字信号以重新捕获原始传输的数据。 因此，可以容易地重新配置无线通信系统内的基站和/或终端用户设备。

公开(公告)号：US07092689B1

公开(公告)日：2006-08-15

申请号：US10660235

申请日：2003-09-11

Applicant: Charles W. Boecker ,  Brian T. Brunn

Inventor： Charles W. Boecker ,  Brian T. Brunn

IPC: H04B1/06

CPC classification number: H04L27/0014 ,  H03L7/0896 ,  H03L7/0898 ,  H04L2027/0055 ,  H04L2027/0067

Abstract: Adjustment circuitry in a phase-locked loop (PLL) adjusts a sampling point to any desired location within a bit period of each bit of received high-speed serial data. The adjustment circuitry, responsive to program control, selectively adds current portions to a charge pump error current output thereby adjusting a feedback signal frequency to shift the serial data sampling point. A plurality of current mirror devices is scaled, with respect to a reference current device, to provide ΔI current portions. A current control module controls the current portions magnitude and a sign of the current portions. The adjustment circuitry further controls charge pump programmable current sources in order to set a desired operating point of the PLL. The programmable current sources are controlled by a bias voltage and a plurality of selectable serial and parallel coupled resistors.

公开(公告)号：US06977959B2

公开(公告)日：2005-12-20

申请号：US10346435

申请日：2003-01-17

Applicant: Brian T. Brunn ,  Ahmed Younis ,  Shahriar Rokhsaz

Inventor： Brian T. Brunn ,  Ahmed Younis ,  Shahriar Rokhsaz

IPC: H03D13/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10 ,  H04L7/033 ,  H04B1/38 ,  H03D3/24

CPC classification number: H04L7/0331 ,  H03D13/003 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/091 ,  H03L7/10

Abstract: A clock recovery circuit that operates at a clock speed equal to one-half the input data rate is presented. The clock recovery circuit uses dual input latches to sample the incoming serial data on both the rising edge and falling edge of a half-rate clock signal to provide equivalent full data rate clock recovery. The clock recovery circuit functions to maintain the half-rate clock transitions in the center of the incoming serial data bits. The clock recovery circuit includes a phase detector, charge pump, controlled oscillation module and a feedback module. The phase detector produces information on the phase and data transitions in the incoming data signal to the charge pump. Generally, the circuit is delay insensitive and receives phase and transition information staggered relative to each other.

Abstract translation: 提出了以等于输入数据速率的一半的时钟速度工作的时钟恢复电路。 时钟恢复电路使用双输入锁存器在半速率时钟信号的上升沿和下降沿对采样的串行数据进行采样，以提供等效的全数据速率时钟恢复。 时钟恢复电路用于保持输入串行数据位中心的半速率时钟转换。 时钟恢复电路包括相位检测器，电荷泵，受控振荡模块和反馈模块。 相位检测器产生关于输入数据信号中的相位和数据转换到电荷泵的信息。 通常，电路是延迟不敏感的，并且相对于彼此交错地接收相位和转换信息。

公开(公告)号：US06417729B1

公开(公告)日：2002-07-09

申请号：US09491538

申请日：2000-01-26

Applicant: Normand T. Lemay ,  Brian T. Brunn ,  John W. MacConnell ,  Eric Sadowski ,  Eric W. Lofstad

Inventor： Normand T. Lemay ,  Brian T. Brunn ,  John W. MacConnell ,  Eric Sadowski ,  Eric W. Lofstad

IPC: H03G320

CPC classification number: G01R21/10 ,  G01R21/14 ,  H03B5/04 ,  H03C1/06 ,  H03F1/345 ,  H03F3/45475 ,  H03G3/004 ,  H03G3/3042 ,  H03L1/02 ,  H03L7/18 ,  Y10S323/907

Abstract: The present invention presents a closed loop system that utilizes a non-linear reference to control a power amplifier's output power in order to obtain a linear transfer function of dB per adjustment step of a reference input. The closed loop system demonstrates that each non-linear stage/step in an automatic gain control system can create a linear closed loop system when using a non-linear reference. The closed loop system of the present invention eliminates the need for a linearization circuit for the system's power detector. The closed loop system may be used with most power amplifiers when linear control in terms of dB vs. adjustment setting of the input reference signal is desired. Output power in terms of dBms can be accurately set in linear steps where power control over a wide dynamic range is desired.

Abstract translation: 本发明提出了一种闭环系统，其利用非线性参考来控制功率放大器的输出功率，以便获得参考输入的每个调节步长的dB的线性传递函数。 闭环系统表明，当使用非线性参考时，自动增益控制系统中的每个非线性阶段/步骤可以创建线性闭环系统。 本发明的闭环系统消除了对系统功率检测器的线性化电路的需要。 当对于输入参考信号的调整设置的dB进行线性控制时，闭环系统可以与大多数功率放大器一起使用。 以dBms为单位的输出功率可以在需要宽动态范围内的功率控制的线性步骤中精确设置。

公开(公告)号：US07784004B1

公开(公告)日：2010-08-24

申请号：US11111135

申请日：2005-04-21

Applicant: Brian T. Brunn ,  Brian K. Seemann

Inventor： Brian T. Brunn ,  Brian K. Seemann

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G01R31/2884

Abstract: Integrated circuits, key components in thousands of products, frequently include thousands and even millions of microscopic transistors and other electrical components. Because of difficulties and costs of fabricating these circuits, circuit designers sometimes ask fabricators to produce skew lots for testing and predicting manufacturing yield. However, conventional skew lots for CMOS circuits, which are based on increasing or decreasing transistor transconductance, are not very useful in testing certain types of analog circuits, such as oscillators. Accordingly, the present inventors developed a new type of skew lot, based on increasing or decreasing gate-to-source capacitance of transistors, or more generally a transistor characteristic other than transconductance. This new type of skew lot is particularly suitable for simulating, testing, and/or making yield predictions for oscillators and other CMOS analog circuits.

Abstract translation: 集成电路，成千上万个产品的关键组件，经常包括数千甚至数百万的微观晶体管和其他电气元件。 由于制造这些电路的困难和成本，电路设计师有时要求制造商生产偏斜批次用于测试和预测制造产量。 然而，基于增加或减少晶体管跨导的CMOS电路的常规偏移批次在测试某些类型的模拟电路（例如振荡器）中不是非常有用的。 因此，本发明人基于晶体管的栅极 - 源极电容的增加或减小，或更通常地是跨导以外的晶体管特性，开发了新型的偏移批次。 这种新型的偏移批次特别适用于振荡器和其他CMOS模拟电路的模拟，测试和/或产量预测。

公开(公告)号：US07142622B1

公开(公告)日：2006-11-28

申请号：US10421248

申请日：2003-04-22

Applicant: Brian T. Brunn ,  Ahmed Younis

Inventor： Brian T. Brunn ,  Ahmed Younis

IPC: H03D3/24

CPC classification number: H03D13/004

Abstract: A multiplying phase detector includes a 1st multiplier, a 2nd multiplier and a phase error generation module. The 1st multiplier is operably coupled to multiple an incoming data stream, which is a random data pattern, with a 1st clock, which is in-phase with the incoming stream of data and is one-half the rate of the incoming stream of data, to produce a 1st product. In this instance, the 1st product represents missing transitions in the incoming stream of data. The 2nd multiplier is operably coupled to multiply the 1st product with the incoming data stream to produce a modified stream of data. The phase error generation module is operably coupled to generate a phase error based on the modified stream of data and a 2nd clock, where the phase error represents a phase offset between the modified stream of data and the 2nd clock.

Abstract translation: 乘法相位检测器包括1乘法器，2乘法器和相位误差产生模块。 1＆lt; ST＆gt;乘法器可操作地耦合到具有1秒时钟的多个输入数据流，其是随机数据模式，其与进入流同步 的数据，并且是传入数据流的一半速率，以产生1 ^{ST 产品。 在这种情况下，1＆lt; ST＆gt;产品表示输入的数据流中的丢失的转换。 2乘法器乘法器可操作地耦合以将第一产品与输入数据流相乘以产生经修改的数据流。 相位误差产生模块可操作地耦合以产生基于经修改的数据流和第二时钟的相位误差，其中相位误差表示修改的数据流与第二时钟之间的相位偏移 nd 时钟。}

公开(公告)号：US07091773B1

公开(公告)日：2006-08-15

申请号：US10900945

申请日：2004-07-28

Applicant: Brian T. Brunn ,  Michael A. Nix

Inventor： Brian T. Brunn ,  Michael A. Nix

IPC: H03F1/36

CPC classification number: H03G11/02 ,  H03F1/34 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2203/45472 ,  H03F2203/45652 ,  H03G11/008

Abstract: A limiting circuit includes an input transconductance stage, an output transconductance stage, a feedback transconductance stage, first and second resistive loads, and a level limiting circuit. The input transconductance stage is operably coupled to convert an input voltage signal into an input current signal. The first resistive load is operably coupled to convert the input current signal and a feedback current signal into an intermediate output voltage signal. The output transconductance stage is operably coupled to convert the intermediate output voltage signal into an output current signal. The second resistive load is operably coupled to convert the output current signal into an output voltage signal. The feedback transconductance stage is operably coupled to produce the feedback current signal based on the output voltage signal. The level limiting module is operably coupled to limit at least one voltage level of the feedback transconductance stage.

Abstract translation: 限制电路包括输入跨导级，输出跨导级，反馈跨导级，第一和第二阻性负载以及电平限制电路。 输入跨导级可操作地耦合以将输入电压信号转换成输入电流信号。 第一电阻负载可操作地耦合以将输入电流信号和反馈电流信号转换成中间输出电压信号。 输出跨导级可操作地耦合以将中间输出电压信号转换成输出电流信号。 第二电阻负载可操作地耦合以将输出电流信号转换成输出电压信号。 反馈跨导级可操作地耦合以产生基于输出电压信号的反馈电流信号。 电平限制模块可操作地耦合以限制反馈跨导级的至少一个电压电平。

公开(公告)号：US07058120B1

公开(公告)日：2006-06-06

申请号：US10051222

申请日：2002-01-18

Applicant: Jinghui Lu ,  Shahriar Rokhsaz ,  Stephen D. Anderson ,  Michael A. Nix ,  Ahmed Younis ,  Michael Ren Kent ,  Yvette P. Lee ,  Firas N. Abughazaleh ,  Brian T. Brunn ,  Moises E. Robinson ,  Kazi S. Hossain

Inventor： Jinghui Lu ,  Shahriar Rokhsaz ,  Stephen D. Anderson ,  Michael A. Nix ,  Ahmed Younis ,  Michael Ren Kent ,  Yvette P. Lee ,  Firas N. Abughazaleh ,  Brian T. Brunn ,  Moises E. Robinson ,  Kazi S. Hossain

IPC: H03K11/00 ,  H04L25/60 ,  H04L25/64

CPC classification number: H03L7/093 ,  H03K5/1565 ,  H03M9/00 ,  H04L7/0004 ,  H04L7/033 ,  H04W4/18

Abstract: A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.

Abstract translation: 收发机包括接收机部分和发射机部分。 接收器部分包括时钟电路，串行到并行模块和补偿。 发射机部分包括时钟电路，并行到串行模块和补偿。 接收器部分和发射器部分内的补偿补偿了时钟控制电路，串行到并行模块和并行到串行模块的集成电路（IC）处理限制和/或集成电路（IC）制造限制，否则 限制收发器可以传输数据的速度。