公开(公告)号：US10771145B2

公开(公告)日：2020-09-08

申请号：US15456086

申请日：2017-03-10

Applicant: SEAKR ENGINEERING, INC.

Inventor： Erik Buehler

IPC: H03K11/00 ,  H04L25/60 ,  H04L25/64 ,  H04B7/185 ,  H04B7/06 ,  H04B1/04 ,  H04B7/08 ,  H03F1/02 ,  H03F3/24

Abstract: A satellite communication system processes a plurality of input signals to generate beamformed signals, drives a plurality of nonlinear power amplifiers with the beamformed input signals to produce RF signals for transmission; and transmits the RF signals with a plurality of Tx antenna elements. Conversion to and from linear signals to and from nonlinear or digitized signals is performed. Temporal or spatial decorrelation of the beamformed signals is employed to reduce the impact of intermodulation products. In some cases the power amplifiers are nonlinear, and can be one-sided or two-sided and produce two or three distinct output levels.

公开(公告)号：US09264102B2

公开(公告)日：2016-02-16

申请号：US14793582

申请日：2015-07-07

Applicant: Pericom Semiconductor Corporation

Inventor： Hung-Yan Cheung ,  Michael Y. Zhang

IPC: H03K11/00 ,  H04L25/60 ,  H04L25/64 ,  H04B3/466 ,  H04B3/14 ,  H04L25/02 ,  H04L25/03

CPC classification number: H04B3/466 ,  H04B3/146 ,  H04L25/0264 ,  H04L25/03878 ,  H04L25/03885

Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

公开(公告)号：US09122314B2

公开(公告)日：2015-09-01

申请号：US13410059

申请日：2012-03-01

Applicant: Yoshimichi Matsuoka ,  Lawrence Lam

Inventor： Yoshimichi Matsuoka ,  Lawrence Lam

IPC: H03K11/00 ,  G06F3/02 ,  H01H13/70

CPC classification number: G06F3/0202 ,  H01H3/125 ,  H01H13/70 ,  H01H13/705 ,  H01H2003/127 ,  H01H2221/00 ,  H01H2221/044

Abstract: Key-input mechanisms are disclosed. An example mechanism includes an arced, resilient keycap, the arc of the keycap having a first central arc angle when un-pressed. The keycap is configured to, when pressed, deform so as to have a second central arc angle, the first central arc angle being greater than the second central arc angle. The keycap is further configured to, when released after being pressed, return to its un-pressed shape having the first central arc angle. The key input mechanism further includes a switch disposed under the keycap. The switch is configured to, when the keycap is pressed, electrically couple two or more circuit traces to indicate a keystroke for the key input mechanism. The switch is further configured to, when the keycap is released, electrically decouple the two or more circuit traces to indicate that the keystroke for the key input mechanism is complete.

Abstract translation: 密钥输入机制被公开。 示例性机构包括弧形弹性键帽，当未按压时，键帽的弧具有第一中心弧角。 键帽被构造成当被按压时变形为具有第二中心弧角，第一中心弧角大于第二中心弧角。 键盖进一步构造成当被按压后释放时返回到具有第一中心弧角的未压制形状。 键输入机构还包括设置在键帽下方的开关。 开关被配置为当按压键帽时，电耦合两个或更多个电路迹线以指示键输入机构的按键。 开关还被配置为当键帽被释放时，电耦合两个或更多个电路迹线以指示键输入机构的按键完成。

公开(公告)号：US08233541B2

公开(公告)日：2012-07-31

申请号：US12056119

申请日：2008-03-26

Applicant: Ming-Chang Liu

Inventor： Ming-Chang Liu

IPC: H03K11/00 ,  H04L25/60 ,  H04L25/00

CPC classification number: G06T3/4053

Abstract: Method and apparatus for improving the quality of super-resolution video imaging by suppressing ringing artifacts, reducing high-frequency noise, reducing blocking artifacts, and smoothing out jagged edges of the image to generate pictures that appear cleaner with less edge degradation. The method operates in a recursive manner within a sequence of low resolution images. Conventional SR processing is primarily enhanced within the invention by adding an artifact suppression section which creates a high frequency component signal ΔSRi having significantly reduced artifacts therein achieving higher quality super-resolution image output. The method can be applied to images and image sequences (video) in monochrome or color and in any desired pixel format. The method can be implemented within image processing devices, in particular those containing programming for executing the described method steps.

Abstract translation: 用于通过抑制振铃伪像，降低高频噪声，减少块伪影并平滑图像的锯齿状边缘以产生出现更清晰且具有较少边缘退化的图像的方法和装置。 该方法以递归方式在低分辨率图像序列内操作。 传统的SR处理在本发明中通过增加伪像抑制部分来增强，该伪像抑制部分产生具有显着减少的伪影的高频分量信号＆amp; SR1，其中实现更高质量的超分辨率图像输出。 该方法可以应用于单色或彩色和任何所需像素格式的图像和图像序列（视频）。 该方法可以在图像处理设备内实现，特别是包含用于执行所描述的方法步骤的编程的设备。

公开(公告)号：US20060093022A1

公开(公告)日：2006-05-04

申请号：US11253750

申请日：2005-10-20

Applicant: Kaoru Ukai ,  Takanobu Mukaide

Inventor： Kaoru Ukai ,  Takanobu Mukaide

IPC: H03K11/00

CPC classification number: H04L12/2803 ,  H04L12/281 ,  H04L12/282 ,  H04L12/2832 ,  H04L69/08 ,  H04L2012/2849

Abstract: A relay device employs a control system which notifies control data indicating its own specification to transmitting equipment to receive data in a form matching to its own specification and acquires control data D13 from receiving equipment employing the control system and connected to a latter stage. The relay device determines whether its own specification is in a higher order or not in comparison a specification indicated by the control data D13 with its own specification, and if it is determined that its own specification is in the higher order, rewrites the control data D13 from the receiving equipment by its own control data D12 to notify it to the transmitting equipment. Thereby, the relay device can reproduce the data from the transmitting equipment in accordance with its own specification. At this time, since the relay device converts the received data from the transmitting equipment to transmit it, even the receiving equipment can reproduce it in accordance with an appropriate specification.

Abstract translation: 中继装置采用一种控制系统，其将指示其自身规格的控制数据通知给发送设备以与其自身的规格相匹配的形式接收数据，并从接收到采用该控制系统的设备并连接到后一级获取控制数据D 13。 比较由控制数据D13表示的具有其自身规格的规格，中继装置确定其自己的规格是否处于更高的阶段，并且如果确定其自己的规范处于较高阶段，则重写控制数据 D 13通过其自己的控制数据D12从接收设备通知其发送设备。 因此，中继设备可以根据其自身的规格从发送设备再现数据。 此时，由于中继装置将来自发送装置的接收数据转换为发送装置，所以即使接收装置也可以根据适当的规格进行再现。

公开(公告)号：US20050286652A1

公开(公告)日：2005-12-29

申请号：US10875570

申请日：2004-06-25

Applicant: Philip MacPhail ,  Jeremy Loraine

Inventor： Philip MacPhail ,  Jeremy Loraine

IPC: H03F1/06 ,  H03F3/217 ,  H03K5/00 ,  H03K7/02 ,  H03K11/00 ,  H04B1/10 ,  H04L25/49

CPC classification number: H03F3/217 ,  H03F3/189 ,  H03F2200/324 ,  H03F2200/351 ,  H03F2200/421 ,  H03F2200/541 ,  H03K7/02 ,  H03K11/00

Abstract: Disclosed is a method and apparatus for amplitude modulation of an RF transmit signal using pulse width modulation to control an amount of energy within each period. The apparatus includes a signal processing circuit with an input port for receiving of information indicative of a carrier frequency and modulation data. The signal processing circuit has a first output port and a second output port for providing of output signals having a phase relationship therebetween. A power amplifier is provided for receiving the output signals and for generating a pulse width modulated signal in dependence thereon.

Abstract translation: 公开了一种使用脉冲宽度调制对RF发射信号进行幅度调制以控制每个周期内的能量的方法和装置。 该装置包括具有用于接收指示载波频率和调制数据的信息的输入端口的信号处理电路。 信号处理电路具有第一输出端口和第二输出端口，用于提供其间具有相位关系的输出信号。 提供功率放大器用于接收输出信号并根据其生成脉宽调制信号。

公开(公告)号：US5768281A

公开(公告)日：1998-06-16

申请号：US633193

申请日：1996-04-16

Applicant: Hideto Takano

Inventor： Hideto Takano

IPC: G11B20/10 ,  H03M7/40 ,  H04B1/66 ,  H04L7/00 ,  H04L13/00 ,  H03K11/00

CPC classification number: H04B1/665

Abstract: The invention provides an ancillary data processing circuit wherein a bit train of ancillary data having a varying data length is converted into another bit train in units of a byte of a rearwardly packed form to make changing of byte boundaries in following processing unnecessary. The ancillary data processing circuit includes a clock masking circuit including a first 3-bit counter which is reset to zero by a synchronism detection signal and counts a first clock signal, a second 3-bit counter which receives the count value of the first counter as a preset value thereof in response to an ancillary data start signal and counts down a second clock signal, a flip-flop which is initialized in response to the ancillary data start signal, reverses the level thereof in response to an overflow signal of the second counter and outputs a masking signal, and a masking circuit which calculates a combination logic of the masking signal and the second clock signal and outputs the second clock signal or the zero level as a third clock signal in response to the level of the masking signal, and an OR circuit which outputs a result of logical ORing of the first and third clock signals as a read clock signal.

Abstract translation: 本发明提供了一种辅助数据处理电路，其中具有变化的数据长度的辅助数据的比特串被转换成以后向打包形式的字节为单位的另一比特串，以使后续处理中的字节边界的改变是不必要的。 辅助数据处理电路包括时钟屏蔽电路，时钟屏蔽电路包括第一3位计数器，其由同步检测信号复位为零并对第一时钟信号进行计数，第二3位计数器接收第一计数器的计数值作为 其响应于辅助数据开始信号的预设值并且对第二时钟信号进行递减计数，响应于辅助数据开始信号被初始化的触发器响应于第二计数器的溢出信号而反转其电平 并输出掩蔽信号，以及掩蔽电路，其根据掩蔽信号的电平计算屏蔽信号和第二时钟信号的组合逻辑，并输出第二时钟信号或零电平作为第三时钟信号;以及 OR电路，其输出第一和第三时钟信号的逻辑或运算结果作为读时钟信号。

公开(公告)号：US5400360A

公开(公告)日：1995-03-21

申请号：US35675

申请日：1993-03-23

Applicant: Alan W. Richards ,  Kenneth R. Talbott ,  Paul R. Smith

Inventor： Alan W. Richards ,  Kenneth R. Talbott ,  Paul R. Smith

IPC: H04L25/49 ,  H03K11/00 ,  H04L25/60 ,  H04L25/64

CPC classification number: H04L25/4902

Abstract: A repeater device in a communication network within a transmission line segment receives a distorted signal from the transmission line and retransmits a modified signal. The repeater includes a detector for activating the device in response to the input of the signal and a logic control in order for directing the signal to the modifying portion of the device. To minimize bit error which may occur as the signal is being transmitted over the network or as the signal is being received by the modifying portion of the repeater, the repeater replaces the leading bit of the signal prior to being retransmitted back to the network.

Abstract translation: 传输线路段内的通信网络中的中继器装置接收来自传输线路的失真信号并重新发送修改的信号。 中继器包括用于响应于信号的输入而激活设备的检测器和用于将信号引导到设备的修改部分的逻辑控制。 为了最小化信号在网络上传输时可能发生的位错误，或者当中继器的修改部分正在接收信号时，中继器将信号的前导位替换回网络。

公开(公告)号：US5166542A

公开(公告)日：1992-11-24

申请号：US563325

申请日：1990-08-07

Applicant: Kunihiro Matsubara ,  Tetsuo Ide

Inventor： Kunihiro Matsubara ,  Tetsuo Ide

IPC: H03H7/01 ,  H03K5/08 ,  H03K5/1252 ,  H03K7/08 ,  H03K11/00

CPC classification number: H03K11/00 ,  H03K5/1252 ,  H03K7/08

Abstract: A signal converter includes a frequency-to-voltage converter for converting a frequency of an input signal received via an input terminal into a control voltage. The input signal contains a noise signal having a frequency different from the frequency of the input signal. The control voltage changes in accordance with a change of the frequency of the input signal. A filter has a variable cutoff frequency so that the noise signal is eliminated from the input signal and outputs a filtered signal. The variable cutoff frequency is changed in accordance with a change of the control voltage so that a change of the variable cutoff frequency follows a change of the frequency of the input signal. A comparator compares the filtered signal with a reference voltage and converts the filtered signal into a pulse signal having a pulse width corresponding to the frequency of the input signal.

公开(公告)号：US4525675A

公开(公告)日：1985-06-25

申请号：US483036

申请日：1983-04-07

Applicant: Carl T. Richmond ,  Thomas A. Butler ,  Joseph E. Andrews, Jr.

Inventor： Carl T. Richmond ,  Thomas A. Butler ,  Joseph E. Andrews, Jr.

IPC: H03D3/00 ,  H03K5/00 ,  H03K9/06 ,  H03K11/00

CPC classification number: H03D3/00

Abstract: Signals to be discriminated are supplied through a controllable attenuator and power splitter to first and second discriminators with response slopes which are equal and of opposite sign. The outputs of the discriminators are summed and a reference signal is subtracted from the sum to produce a control signal which adjusts the input attenuator to maintain the amplitude of the input signal constant. The outputs of the discriminators are also subtracted to provide an output signal which is a linear function of frequency and independent of input amplitude.

Abstract translation: 要鉴别的信号通过可控衰减器和功率分配器提供给具有相反和相反符号的响应斜率的第一和第二鉴别器。 将鉴别器的输出相加，并从和中减去参考信号，以产生调节输入衰减器以控制输入信号的幅度恒定的控制信号。 鉴别器的输出也被减去以提供一个输出信号，它是频率的线性函数，与输入幅度无关。