公开(公告)号：US20240103871A1

公开(公告)日：2024-03-28

申请号：US17955379

申请日：2022-09-28

申请人： Jason Brandt ,  Ittai Anati ,  Andreas Kleen ,  David Sheffield

发明人： Jason Brandt ,  Ittai Anati ,  Andreas Kleen ,  David Sheffield

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30101 ,  G06F9/30189

摘要： Techniques for CPUID are described. In some examples, a CPUID instruction is to include at least one field for an opcode, the opcode to indicate execution circuitry is to return processor identification and feature information determined by input into a first register and a second register, wherein the processor identification and feature information is to include an indication of an availability of a second execution mode that at least deprecates features of a first execution.

公开(公告)号：US20240103869A1

公开(公告)日：2024-03-28

申请号：US17955347

申请日：2022-09-28

申请人： Andreas Kleen ,  Jason Brandt ,  Ittai Anati ,  David Sheffield ,  Toby Opferman ,  Ian Hanschen ,  Xiang Zou ,  Terry Parks

发明人： Andreas Kleen ,  Jason Brandt ,  Ittai Anati ,  David Sheffield ,  Toby Opferman ,  Ian Hanschen ,  Xiang Zou ,  Terry Parks

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30189

摘要： Techniques for using CPUID for showing features that are deprecated are described. In some examples, CPUID is to include at least one field for an opcode, one or more fields to identify a source operand which is to store a LSL selector value, and one or more fields to identify a destination register operand, wherein the opcode is to indicate that execution circuitry is to, when the single instruction has been enabled by a setting of a bit in a control register, write a LSL value stored in the control register to the destination operand when the LSL selector value of the first source register operand matches a LSL selector value stored in the control register, and set a flag in a flags register.

公开(公告)号：US09384037B2

公开(公告)日：2016-07-05

申请号：US13993628

申请日：2013-03-14

申请人： Andreas Kleen

发明人： Andreas Kleen

IPC分类号： G06F12/02 ,  G06F9/46 ,  G06F9/06 ,  G06F12/08 ,  G06F12/14 ,  G06F17/30

CPC分类号： G06F9/467 ,  G06F9/06 ,  G06F9/526 ,  G06F12/0261 ,  G06F12/0269 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/1466 ,  G06F17/30327 ,  G06F2212/1048

摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for memory object reference count management with improved scalability based on transactional reference count elision. The device may include a hardware transactional memory processor configured to maintain a read-set associated with a transaction and to abort the transaction in response to a modification of contents of the read-set by an entity external to the transaction; and a code module configured to: enter the transaction; locate the memory object; read the reference count associated with the memory object, such that the reference count is added to the read-set associated with the transaction; access the memory object; and commit the transaction.

摘要翻译： 通常，本公开提供了用于存储器对象引用计数管理的系统，设备，方法和计算机可读介质，其基于事务参考计数检测具有改进的可扩展性。 该设备可以包括硬件事务存储器处理器，其被配置为维护与事务相关联的读取集合并且响应于该事务外部的实体对该读取集合的内容的修改来中止该事务; 以及代码模块，被配置为：输入所述交易; 定位内存对象; 读取与存储器对象相关联的引用计数，使得引用计数被添加到与事务相关联的读取集合; 访问内存对象; 并提交交易。

公开(公告)号：US20190213120A1

公开(公告)日：2019-07-11

申请号：US15868819

申请日：2018-01-11

申请人： Omid Azizi ,  Amin Firoozshahian ,  Andreas Kleen ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert ,  Eric Gouldey

发明人： Omid Azizi ,  Amin Firoozshahian ,  Andreas Kleen ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert ,  Eric Gouldey

IPC分类号： G06F12/02 ,  G06F9/50 ,  G06F3/06

CPC分类号： G06F12/0246 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0641 ,  G06F3/065 ,  G06F9/5016 ,  G06F12/0292

摘要： Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

公开(公告)号：US20140317352A1

公开(公告)日：2014-10-23

申请号：US13993628

申请日：2013-03-14

申请人： Andreas Kleen

发明人： Andreas Kleen

IPC分类号： G06F9/46 ,  G06F12/14 ,  G06F17/30 ,  G06F12/02 ,  G06F12/08

CPC分类号： G06F9/467 ,  G06F9/06 ,  G06F9/526 ,  G06F12/0261 ,  G06F12/0269 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/1466 ,  G06F17/30327 ,  G06F2212/1048

摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for memory object reference count management with improved scalability based on transactional reference count elision. The device may include a hardware transactional memory processor configured to maintain a read-set associated with a transaction and to abort the transaction in response to a modification of contents of the read-set by an entity external to the transaction; and a code module configured to: enter the transaction; locate the memory object; read the reference count associated with the memory object, such that the reference count is added to the read-set associated with the transaction; access the memory object; and commit the transaction.

摘要翻译： 通常，本公开提供了用于存储器对象引用计数管理的系统，设备，方法和计算机可读介质，其基于事务参考计数检测具有改进的可扩展性。 该设备可以包括硬件事务存储器处理器，其被配置为维护与事务相关联的读取集合并且响应于该事务外部的实体对该读取集合的内容的修改来中止该事务; 以及代码模块，被配置为：输入所述交易; 定位内存对象; 读取与存储器对象相关联的引用计数，使得引用计数被添加到与事务相关联的读取集合; 访问内存对象; 并提交交易。

公开(公告)号：US20240103870A1

公开(公告)日：2024-03-28

申请号：US17955364

申请日：2022-09-28

申请人： Andreas Kleen ,  David Sheffield ,  Jason Brandt ,  Ittai Anati

发明人： Andreas Kleen ,  David Sheffield ,  Jason Brandt ,  Ittai Anati

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30032 ,  G06F9/3005

摘要： Techniques for supporting a far jump and IRET are described. An example far jump instruction support includes support for a single instruction to include at least one field for an opcode and one or more fields for an operand, wherein the opcode is to indicate execution circuitry is to perform a far jump and the operand is to specify an address to be jumped to, wherein an operand size attribute of the instance of the instruction is 32-bit or greater and the instruction has been enabled by a setting of a bit in a compatibility control register.

公开(公告)号：US20190042461A1

公开(公告)日：2019-02-07

申请号：US15958591

申请日：2018-04-20

申请人： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

发明人： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/0862 ,  G06F9/38

摘要： A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.

公开(公告)号：US20230401061A1

公开(公告)日：2023-12-14

申请号：US18126920

申请日：2023-03-27

申请人： Ashok RAJ ,  Andreas KLEEN ,  Gilbert NEIGER ,  Beeman STRONG ,  Jason BRANDT ,  Rupin VAKHARWALA ,  Jeff HUXEL ,  Larisa NOVAKOVSKY ,  Ido OUZIEL ,  Sarathy JAYAKUMAR

发明人： Ashok RAJ ,  Andreas KLEEN ,  Gilbert NEIGER ,  Beeman STRONG ,  Jason BRANDT ,  Rupin VAKHARWALA ,  Jeff HUXEL ,  Larisa NOVAKOVSKY ,  Ido OUZIEL ,  Sarathy JAYAKUMAR

IPC分类号： G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

CPC分类号： G06F9/30098 ,  G06F15/80 ,  G06F9/5005 ,  G06F9/4812

摘要： An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

公开(公告)号：US20210357221A1

公开(公告)日：2021-11-18

申请号：US17359337

申请日：2021-06-25

申请人： Ashok RAJ ,  Andreas KLEEN ,  Gilbert NEIGER ,  Beeman STRONG ,  Jason BRANDT ,  Rupin VAKHARWALA ,  Jeff HUXEL ,  Larisa NOVAKOVSKY ,  Ido OUZIEL ,  Sarathy JAYAKUMAR

发明人： Ashok RAJ ,  Andreas KLEEN ,  Gilbert NEIGER ,  Beeman STRONG ,  Jason BRANDT ,  Rupin VAKHARWALA ,  Jeff HUXEL ,  Larisa NOVAKOVSKY ,  Ido OUZIEL ,  Sarathy JAYAKUMAR

IPC分类号： G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

摘要： An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

公开(公告)号：US20190303281A1

公开(公告)日：2019-10-03

申请号：US15941468

申请日：2018-03-30

申请人： Amin Firoozshahian ,  Vedaraman Greetha ,  Andreas Kleen ,  Stephen Van Doren ,  Omid Azizi ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert

发明人： Amin Firoozshahian ,  Vedaraman Greetha ,  Andreas Kleen ,  Stephen Van Doren ,  Omid Azizi ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert

IPC分类号： G06F12/02 ,  G06F12/06

摘要： Various systems and methods for controlling memory traffic flow rate are described herein. A system for computer memory management, the system comprising: rate control circuitry to: receive a rate exceeded signal from monitoring circuitry, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold; receive a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.