-
公开(公告)号：US09601199B2
公开(公告)日：2017-03-21
申请号：US12842958
申请日：2010-07-23
IPC分类号： G11C15/00
CPC分类号： G06F12/0811 , G06F12/0826 , G06F12/0862 , G06F2212/283 , G06F2212/602 , G06F2212/622 , G11C15/00
摘要： Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain.Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element. A local state associated with a selected iterator register is generated by performing one or more register operations relating to the selected iterator register and involving pointers in the pointer fields of the selected iterator register. A pointer-linked data structure is updated in the memory system according to the local state.
-
公开(公告)号：US20190303281A1
公开(公告)日：2019-10-03
申请号：US15941468
申请日：2018-03-30
申请人： Amin Firoozshahian , Vedaraman Greetha , Andreas Kleen , Stephen Van Doren , Omid Azizi , Mahesh Madhav , Mahesh Maddury , Chandan Egbert
发明人： Amin Firoozshahian , Vedaraman Greetha , Andreas Kleen , Stephen Van Doren , Omid Azizi , Mahesh Madhav , Mahesh Maddury , Chandan Egbert
摘要： Various systems and methods for controlling memory traffic flow rate are described herein. A system for computer memory management, the system comprising: rate control circuitry to: receive a rate exceeded signal from monitoring circuitry, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold; receive a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.
-
公开(公告)号：US20190213120A1
公开(公告)日：2019-07-11
申请号：US15868819
申请日：2018-01-11
申请人： Omid Azizi , Amin Firoozshahian , Andreas Kleen , Mahesh Madhav , Mahesh Maddury , Chandan Egbert , Eric Gouldey
发明人： Omid Azizi , Amin Firoozshahian , Andreas Kleen , Mahesh Madhav , Mahesh Maddury , Chandan Egbert , Eric Gouldey
CPC分类号： G06F12/0246 , G06F3/0604 , G06F3/0608 , G06F3/0641 , G06F3/065 , G06F9/5016 , G06F12/0292
摘要： Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.
-
公开(公告)号：US20110010347A1
公开(公告)日：2011-01-13
申请号：US12842958
申请日：2010-07-23
CPC分类号： G06F12/0811 , G06F12/0826 , G06F12/0862 , G06F2212/283 , G06F2212/602 , G06F2212/622 , G11C15/00
摘要： Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain.Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element. A local state associated with a selected iterator register is generated by performing one or more register operations relating to the selected iterator register and involving pointers in the pointer fields of the selected iterator register. A pointer-linked data structure is updated in the memory system according to the local state.
摘要翻译： 公开了从计算机存储器系统加载数据。 提供了一种存储器系统，其中存储在存储器系统中的一些或全部数据被组织为一个或多个指针连接的数据结构。 提供一个或多个迭代器寄存器。 第一指针链被加载，具有两个或多个指针，其将所选择的指针链接数据结构的第一元素导向所选择的迭代器寄存器。 第二指针链被加载，具有两个或多个指针，导向所选择的指针相关联的数据结构的第二元素到所选择的迭代器寄存器。 第二指针链的加载重新使用与第二指针链共同的第一指针链的部分。 公开了存储在计算机存储器系统中的数据的修改。 提供了一种存储系统。 提供一个或多个迭代器寄存器，其中迭代器寄存器每个包括两个或更多个指针字段，用于存储形成指向数据元素的指针链的两个或更多个指针。 通过执行与所选择的迭代器寄存器相关的一个或多个寄存器操作并且涉及所选择的迭代器寄存器的指针字段中的指针来生成与所选迭代器寄存器相关联的本地状态。 根据本地状态在存储器系统中更新指针关联的数据结构。
-
公开(公告)号：US20190354487A1
公开(公告)日：2019-11-21
申请号：US15980523
申请日：2018-05-15
申请人： Vijay Bahirji , Amin Firoozshahian , Mahesh Madhav , Toby Opferman , Omid Azizi
发明人： Vijay Bahirji , Amin Firoozshahian , Mahesh Madhav , Toby Opferman , Omid Azizi
IPC分类号： G06F12/1009
摘要： A system for computer memory management that implements a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes; a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and processing circuitry to: scan each entry in the per-page tracking table and, for each entry: determine an amount of memory released if the memory page related with the entry is swapped; aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.
-
公开(公告)号：US20190212935A1
公开(公告)日：2019-07-11
申请号：US15868787
申请日：2018-01-11
申请人： Chandan Egbert , Amin Firoozshahian , Mahesh Maddury , John Stevenson , Henk Neefs , Omid Azizi
发明人： Chandan Egbert , Amin Firoozshahian , Mahesh Maddury , John Stevenson , Henk Neefs , Omid Azizi
IPC分类号： G06F3/06 , G06F12/02 , G06F12/0811 , G06F12/084 , G06F12/0868
摘要： Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.
-
公开(公告)号：US20190042461A1
公开(公告)日：2019-02-07
申请号：US15958591
申请日：2018-04-20
申请人： Rupin Vakharwala , Amin Firoozshahian , Stephen Van Doren , Rajesh Sankaran , Mahesh Madhav , Omid Azizi , Andreas Kleen , Mahesh Maddury , Ashok Raj
发明人： Rupin Vakharwala , Amin Firoozshahian , Stephen Van Doren , Rajesh Sankaran , Mahesh Madhav , Omid Azizi , Andreas Kleen , Mahesh Maddury , Ashok Raj
IPC分类号： G06F12/1009 , G06F3/06 , G06F12/0862 , G06F9/38
摘要： A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.017 秒)
