公开(公告)号：US12133379B2

公开(公告)日：2024-10-29

申请号：US17235577

申请日：2021-04-20

申请人： SK hynix Inc.

发明人： Nam Jae Lee

IPC分类号： H10B41/27 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC分类号： H10B41/27 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

摘要： There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes: a channel structure including a first pillar part and a second pillar part extending from the first pillar part; a blocking insulating layer surrounding a sidewall of the first pillar part; a data storage layer disposed between the first pillar part and the blocking insulating layer; an upper select line overlapping with an end portion of the blocking insulating layer and an end portion of the data storage layer, which face in an extending direction of the second pillar part, the upper select line surrounding a sidewall of the second pillar part; and a tunnel insulating layer disposed between the first pillar part and the data storage layer, the tunnel insulating layer extending between the second pillar part and the upper select line.

公开(公告)号：US12133012B2

公开(公告)日：2024-10-29

申请号：US17982952

申请日：2022-11-08

申请人： SK hynix Inc.

发明人： Yu Jin Park ,  Han Sol Park

IPC分类号： H04N25/778 ,  H01L27/146 ,  H04N25/78

CPC分类号： H04N25/778

摘要： The present technology relates to an image sensor. The image sensor according to an embodiment may include a pixel array in which a plurality of pixels are connected through common lines, an internal amplifier configured to amplify a signal of a target pixel selected from among the plurality of pixels, switches configured to control a connection between the target pixel and floating diffusion nodes of candidate pixels having the same column address as the target pixel among the plurality of pixels, and a controller configured to output control signals for controlling the switches.

公开(公告)号：US12126357B2

公开(公告)日：2024-10-22

申请号：US18085236

申请日：2022-12-20

申请人： SK hynix Inc.

发明人： Seon Woo Hwang ,  Seong Jin Kim ,  Jung Hwan Ji

IPC分类号： H03M13/11 ,  H03M13/00

CPC分类号： H03M13/1111 ,  H03M13/6356

摘要： In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.

公开(公告)号：US12119822B2

公开(公告)日：2024-10-15

申请号：US18450749

申请日：2023-08-16

申请人： SK hynix Inc.

发明人： Young Ouk Kim ,  Gyu Tae Park

IPC分类号： H03K3/017 ,  H03K5/00 ,  H03K5/01 ,  H03L7/081

CPC分类号： H03K3/017 ,  H03K5/01 ,  H03L7/0812 ,  H03K2005/00019

摘要： A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.

公开(公告)号：US12112468B2

公开(公告)日：2024-10-08

申请号：US17163051

申请日：2021-01-29

申请人： Electronics and Telecommunications Research Institute

发明人： Hye-Jin Kim ,  Suyoung Chi

IPC分类号： G06K9/00 ,  G06N20/00 ,  G06T7/00 ,  G06T7/50

CPC分类号： G06T7/0006 ,  G06N20/00 ,  G06T7/50 ,  G06T2207/20081 ,  G06T2207/30108

摘要： An apparatus for detecting a dimension error obtains an image of a target object, estimates dimensional data for a region of interest (ROI) for which dimensions are to be measured from the image of the target object using a learned dimensional measurement model, and determines whether there is a dimension error in the ROI from the estimated dimension data using a learned dimension error determination model.

公开(公告)号：US12101485B2

公开(公告)日：2024-09-24

申请号：US17787853

申请日：2020-12-23

申请人： Electronics and Telecommunications Research Institute

发明人： Won Sik Cheong ,  Kug Jin Yun

IPC分类号： H04N19/136 ,  H04N19/172 ,  H04N19/174

CPC分类号： H04N19/136 ,  H04N19/172 ,  H04N19/174

摘要： Disclosed herein are a video encoding/decoding method and apparatus. The video decoding method according to the present disclosure includes: when a current picture is composed of a plurality of tiles and a current tile among the plurality of tiles is partitioned into a plurality of slices, decoding information on the number of slices in tile that indicates the number of the plurality of slices comprised in the current tile; decoding information on a slice height in tile that indicates a height of the plurality of slices comprised in the current tile; and determining the number of the plurality of slices comprised in the current tile and a height of the plurality of slices comprised in the current tile.

公开(公告)号：US12094536B2

公开(公告)日：2024-09-17

申请号：US17833013

申请日：2022-06-06

申请人： SK hynix Inc.

发明人： Hyung Jin Choi

IPC分类号： G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C16/24 ,  G11C16/3459

摘要： A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array through word lines and bit lines, and suitable for performing one or more program loops on memory cells that are coupled to a selected word line of the word lines, each program loop including a program voltage application operation and a program verification operation; and a program control circuit suitable for controlling the peripheral circuit to decrease a level of a precharge voltage that is applied to the bit lines during the program verification operation when the number of program loops that are performed is greater than a reference number.

公开(公告)号：US12091845B2

公开(公告)日：2024-09-17

申请号：US17785806

申请日：2020-12-15

申请人： THE SL CO., LTD.

发明人： Kyeong Keun Song ,  Jong Geun Lim

IPC分类号： E03C1/044 ,  E03C1/04 ,  E03C1/05

CPC分类号： E03C1/044 ,  E03C1/041 ,  E03C1/057

摘要： The faucet control device and method, and faucet are disclosed The faucet control device has a first and a second flow sensors measuring quantity of hot and cold water respectively, a first and a second temperature sensors measuring temperature of hot and cold water respectively, a heating tank heating hot water supplied from a hot water pile with a heater installed therein and storing heated water, a third temperature sensor measuring temperature of the heated water, a hot water direct supplying pipe outputting the hot water supplied from a hot water pipe, a electronic valve outputting mixed water by selectively mixing the heated water, the hot water and the cold water, and a controller controlling operation of the heater based on the temperature of the heated water and controlling opening amount of the electronic valve to make quantity and temperature of discharged water equal to target quantity and temperature.

公开(公告)号：US12087686B2

公开(公告)日：2024-09-10

申请号：US18320818

申请日：2023-05-19

申请人： SK hynix Inc.

发明人： Jin Won Lee ,  Nam Jae Lee

IPC分类号： H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

摘要： There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.

公开(公告)号：US12080333B2

公开(公告)日：2024-09-03

申请号：US17577289

申请日：2022-01-17

申请人： SK hynix Inc.

发明人： Choung Ki Song

IPC分类号： G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/36

CPC分类号： G11C11/40618 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/36

摘要： A semiconductor system including: an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count; and a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information.