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公开(公告)号：US09271163B1
公开(公告)日：2016-02-23
申请号：US13909537
申请日：2013-06-04
申请人： PMC-SIERRA, US, INC.
CPC分类号： H04B17/318 , H04B1/0007 , H04B1/16 , H04L1/0045 , H04L25/067 , H04L27/06 , H04W24/00
摘要： The peak level of a high frequency analog signal in an RF receiver is detected by a system which samples the signal and compares it against a static threshold, generating an above/below status. The system is implemented with a sampler of sufficient aperture bandwidth to capture the signal in question, operated at a clock frequency, dynamically chosen as a function of fLO (local oscillator frequency) and the desired fIF (intermediate frequency), to minimize in-band intermodulation products. The sampler produces kickback intermodulation products that are positioned out-of-band, or are of low enough power in-band so as to be inconsequential. Samples are taken for a statistically significant period of time, and the status is used to adapt the threshold to systematically determine the peak amplitude of the signal being observed.
摘要翻译： RF接收机中的高频模拟信号的峰值电平由对信号进行采样并将其与静态阈值进行比较的系统检测，产生上/下状态。 该系统采用具有足够的孔径带宽的采样器来捕获在时钟频率下运行的所述信号，其作为fLO（本地振荡器频率）和期望的fIF（中间频率）的函数动态选择，以使带内最小化 互调产品。 采样器产生位于带外的或者具有足够低功率带内的反冲互调产物，从而无关紧要。 样本采集统计学显着的时间段，状态用于调整阈值以系统地确定观察到的信号的峰值幅度。
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2.发明授权Methods and apparatus for SAS controllers with link list based target queues 有权具有基于链路列表的目标队列的SAS控制器的方法和装置公开(公告)号：US09256521B1
公开(公告)日：2016-02-09
申请号：US13288637
申请日：2011-11-03
申请人： Raymond Lam , Ivy Chow
发明人： Raymond Lam , Ivy Chow
摘要： A controller comprising a transport layer, an internal memory, and a link list manager block. The internal memory stores pending instruction entries. The link list manager block is configured to read instructions stored in an external memory, update an active vector, the active vector for storing indications of instructions from the external memory; update the pending instruction entries in the internal memory; and update the instructions stored in the external memory. The link list manager block configured to dispatch a instruction from the pending instruction entries in the internal memory to the transport layer.
摘要翻译： 控制器，包括传输层，内部存储器和链路列表管理器块。 内部存储器存储未决指令条目。 链接列表管理器块被配置为读取存储在外部存储器中的指令，更新活动向量，用于存储来自外部存储器的指令的指示的活动向量; 更新内部存储器中的挂起指令条目; 并更新存储在外部存储器中的指令。 链路列表管理器块被配置为将指令从内部存储器中的待决指令条目分派到传输层。
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公开(公告)号：US09235488B2
公开(公告)日：2016-01-12
申请号：US14168222
申请日：2014-01-30
申请人： PMC-SIERRA US, INC.
CPC分类号： G06F11/2215 , G06F11/1012 , H03M13/1111 , H03M13/3905 , H03M13/3927
摘要： A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.
摘要翻译： 一种随机噪声生成模块，用于产生用于测试非易失性存储器存储模块的纠错电路的噪声LLR。 所述随机噪声生成模块包括用于产生一个或多个系数的系数发生器，所述多个系数中的每一个与多个区域中的一个区域相关联，所述多个区域定义根据在概率分布曲线下的区域成比例地划分的线性空间 非易失性存储器存储模块。 随机噪声生成模块还包括用于生成线性随机数的线性随机数发生器和用于将线性随机数与多个系数中的一个或多个进行比较的比较器，以识别概率分布曲线的多个区域的区域 其中线性随机数属于产生用于测试非易失性存储器存储模块的纠错电路的噪声LLR。
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公开(公告)号：US09229433B1
公开(公告)日：2016-01-05
申请号：US14552241
申请日：2014-11-24
申请人： PMC-SIERRA US, INC.
发明人： Mark Hiebert , Derek J. W. Ho
CPC分类号： G04F10/005 , G04F10/00 , G06F1/12 , H03L7/0805 , H03L7/087 , H03L7/1976 , H03L7/23 , H03L7/235 , H03M1/00 , H03M1/12 , H03M1/1255 , H03M2201/4233 , H04L7/0331
摘要： Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.
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公开(公告)号：US09225507B1
公开(公告)日：2015-12-29
申请号：US13910016
申请日：2013-06-04
申请人： PMC-SIERRA US, INC.
CPC分类号： G04F10/005 , G04F10/00 , G06F1/12 , H03L7/0805 , H03L7/087 , H03L7/1976 , H03L7/23 , H03L7/235 , H03M1/00 , H03M1/12 , H03M1/1255 , H03M2201/4233 , H04L7/0331
摘要： Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.
摘要翻译： 提供了一种用于使由第一射频（RF）路径中的可控LO时钟发生器产生的第一本地振荡器（LO）时钟与第二RF路径中的第二LO时钟对准的方法和装置。 该装置包括被配置为在第一和第二RF路径之间交换同步时钟的同步信道，被配置为测量第一和第二LO时钟之间的相位对准的相位检测器，以及被配置为使用 相位对准。 还提供了一个时间到数字转换器。 数字转换器的时间包括用于以第三时钟对第一和第二输入时钟进行采样的D触发器，以及被配置为同步地增加所得样本并产生表示第一和第二时钟之间的延迟的数字比例值的计数器。
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6.发明授权Method and system for decoding encoded data stored in a non-volatile memory 有权用于解码存储在非易失性存储器中的编码数据的方法和系统公开(公告)号：US09170876B1
公开(公告)日：2015-10-27
申请号：US14144857
申请日：2013-12-31
申请人： PMC-Sierra US, Inc.
CPC分类号： G06F11/1048
摘要： A method of decoding a primary codeword and a set of secondary codewords stored in a non-volatile memory (NVM), which includes reading, from the NVM, the primary codeword and all the secondary codewords and storing them in a second memory. The primary codeword is then read from the second memory and decoded, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector. When the decoding of the primary codeword is unsuccessful: each secondary codeword of the set of secondary codewords is read from the second memory and decoded, utilizing a hard-decision decoder, to identify and correct errored data bits in the each secondary codeword and to determine a location of each errored data bit in the primary codeword. An adjusted LLR vector is generated by adjusting the LLR for each primary codeword data bit based on the determined locations of the errored data bits in the primary codeword.
摘要翻译： 解码存储在非易失性存储器（NVM）中的主码字和一组次码字的方法，其包括从NVM读取主码字和所有次码字，并将它们存储在第二存储器中。 然后，基于对数似然比（LLR）向量，利用软判决解码器从第二存储器读取主码字并进行解码。 当主代码字的解码不成功时：从第二存储器中读取第二码字集合中的每个辅助码字，并利用硬判决解码器解码以识别和校正每个次码字中的错误数据位并确定 主码字中每个错误数据位的位置。 通过基于所确定的主码字中的错误数据位的位置来调整每个主码字数据位的LLR来生成经调整的LLR向量。
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7.发明授权Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system 有权基于LDPC码的装置和方法，用于调整存储器系统中可校正的原始误码率限制公开(公告)号：US09092353B1
公开(公告)日：2015-07-28
申请号：US13752885
申请日：2013-01-29
申请人： PMC-SIERRA US, INC.
CPC分类号： G06F11/1068 , G06F11/1008 , G11C29/52 , H03M13/11 , H03M13/1108 , H03M13/1111 , H03M13/116 , H03M13/2957 , H03M13/3715 , H03M13/45
摘要： Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated for message values can be changed during soft-decision decoding. The correctable raw bit error rate is adjusted by changing the code-rate within the memory system while making virtual adjustments to the same encoder and decoder.
摘要翻译： 用于校正从存储器单元读取的数据中的错误的系统和方法包括存储器控制器，其包括编码器和解码器。 存储器控制器被配置为调整可校正的原始误码率限制，以校正从存储器单元读取的数据中发生的不同位错误率。 通过切换硬判决解码和软判决解码之间的解码来调整可校正的原始误码率限制，其中在软判决解码期间可以改变分配给消息值的软比特数。 通过在对同一编码器和解码器进行虚拟调整的同时改变存储器系统内的码率来调整可校正的原始误码率。
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8.发明授权Method and system for transporting constant bit rate clients across a packet interface 有权用于在分组接口上传输恒定比特率客户端的方法和系统公开(公告)号：US09019997B1
公开(公告)日：2015-04-28
申请号：US13843459
申请日：2013-03-15
申请人： PMC-Sierra US, Inc.
CPC分类号： H04B10/07 , H04J3/0658 , H04J3/0697 , H04J3/1617 , H04J3/1664 , H04Q11/04 , H04Q2213/1301
摘要： This disclosure describes a method and apparatus for signaling the phase and frequency of OTN and Constant Bit Rate (CBR) clients in an OTN network. The principles discussed are applicable when multiple stages of OTN multiplexing and demultiplexing are utilized. They are also applicable for use with the Generic Mapping Procedure (GMP) and Asynchronous Mapping Procedure (AMP). A method to use the phase and frequency of an ODUk/ODUflex to adjust a local reference clock to enable the recovery of the phase and frequency of a CBR client demapped from the ODUk/ODUflex is described.
摘要翻译： 本公开描述了用于在OTN网络中用信号通知OTN和恒定比特率（CBR）客户端的相位和频率的方法和装置。 所讨论的原理适用于使用多级OTN复用和解复用的多个阶段。 它们也适用于通用映射过程（GMP）和异步映射过程（AMP）。 描述了使用ODUk / ODUflex的相位和频率来调整本地参考时钟以使得能够恢复从ODUk / ODUflex解映射的CBR客户端的相位和频率的方法。
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公开(公告)号：US08879615B1
公开(公告)日：2014-11-04
申请号：US13830841
申请日：2013-03-14
申请人： PMC-Sierra US, Inc.
发明人： Mathieu Gagnon
CPC分类号： H04L25/03885 , H04L25/03305 , H04L2025/03356
摘要： An equalization adaptation circuit comprises an equalizer, a transition determination circuit, a phase error circuit, a sequence recovery circuit, a phase error accumulator circuit, a transition accumulator circuit, and a controller circuit. The equalizer has adjustable parameters. The transition determination circuit determines observed transitions in an equalized signal output from the equalizer. A phase error circuit determines phase errors of the observed transitions. A sequence recovery circuit generates recovered digital data sequences. A phase error accumulator circuit accumulates the phase errors in respective association with pre-defined patterns matching the recovered digital data sequences containing observed transitions corresponding to the phase errors. A transition accumulator circuit accumulates a number of the observed transitions. A controller circuit controls the adjustable parameters of the equalizer based upon the accumulated phase errors and number of observed transitions.
摘要翻译： 均衡适配电路包括均衡器，转换判定电路，相位误差电路，序列恢复电路，相位误差累积器电路，转换累加器电路和控制器电路。 均衡器具有可调参数。 转换确定电路确定从均衡器输出的均衡信号中观察到的转变。 相位误差电路确定观察到的转变的相位误差。 序列恢复电路产生恢复的数字数据序列。 相位误差累加器电路分别与相应于预定义模式的相位误差相加，该预定模式与包含与相位误差对应的观测转换的恢复数字数据序列相匹配。 过渡累加器电路累积许多观察到的过渡。 控制器电路基于累积的相位误差和观测到的转换次数来控制均衡器的可调参数。
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公开(公告)号：US08843671B1
公开(公告)日：2014-09-23
申请号：US13406390
申请日：2012-02-27
CPC分类号： G06F3/0631 , G06F3/061 , G06F3/067 , G06F3/0683
摘要： Various embodiments of the invention provide resource management of available data bandwidth of a SAS system in a non-uniform way. In certain embodiments, arbitration wait time values are adaptively modified to achieve a specified performance quota for a link.
摘要翻译： 本发明的各种实施例以不均匀的方式提供SAS系统的可用数据带宽的资源管理。 在某些实施例中，自适应地修改仲裁等待时间值以实现链路的指定性能配额。
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