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公开(公告)号：US11996444B2
公开(公告)日：2024-05-28
申请号：US17844344
申请日：2022-06-20
发明人： Guk Hwan Kim
IPC分类号： H01L29/06 , H01L27/02 , H01L29/40 , H01L29/417 , H01L29/423
CPC分类号： H01L29/0638 , H01L27/0251 , H01L29/401 , H01L29/41775 , H01L29/42364
摘要： A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.
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公开(公告)号：US11855184B2
公开(公告)日：2023-12-26
申请号：US17337596
申请日：2021-06-03
发明人： Soo Chang Kang , Seong Jo Hong
IPC分类号： H01L29/66 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L21/768 , H01L29/417 , H01L27/02 , H01L21/266 , H01L29/739 , H01L29/866
CPC分类号： H01L29/66734 , H01L21/76897 , H01L27/0255 , H01L29/0696 , H01L29/0865 , H01L29/1095 , H01L29/41741 , H01L29/7808 , H01L29/7813 , H01L21/266 , H01L29/7397 , H01L29/866
摘要： A method for manufacturing a power semiconductor device includes forming a drift region in a substrate, forming a trench in the drift region, forming a gate insulating layer in the trench, depositing a conductive material on the substrate, forming a gate electrode in the trench, forming a body region in the substrate, forming a highly doped source region in the body region, forming an insulating layer that covers the gate electrode, etching the insulating layer to open the body region, implanting a dopant into a portion of the body region to form a highly doped body contact region, so that the highly doped source region and the highly doped body contact region are alternately formed in the body region; and forming a source electrode on the highly doped body contact region and the highly doped source region.
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公开(公告)号：US20230283269A1
公开(公告)日：2023-09-07
申请号：US17968339
申请日：2022-10-18
发明人： Chelho CHUNG , Gilsung ROH
IPC分类号： H03K5/133
CPC分类号： H03K5/133
摘要： A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval.
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4.发明公开公开(公告)号：US20230223935A1
公开(公告)日：2023-07-13
申请号：US18188144
申请日：2023-03-22
发明人： Jung Hoon SUL , Dong Il SEO
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F2203/45248 , H03F2200/552
摘要： A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.
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公开(公告)号：US11676680B2
公开(公告)日：2023-06-13
申请号：US17581042
申请日：2022-01-21
发明人： Sangsu Park
CPC分类号： G11C29/42 , G11C29/1201 , G11C29/18 , G11C29/4401 , G11C29/76 , G11C2029/3602
摘要： A method for dynamically handling the failure of the static random-access memory (SRAM) dynamic failure handling system using a cyclic redundancy check (CRC) includes obtaining a write data; determining a write address; storing the write data at the write address of a frame memory which is composed of the SRAM and includes a real address area and a spare address area which are distinguished from each other; storing, in response to the write address, a write cyclic redundancy check (CRC) generated by performing a CRC calculation on the write data; determining a read address; reading a read data from the read address of the frame memory; determining whether, based on the A CRC remainder W_CRC corresponding to the read address and the read data, a CRC error occurs, and generating an error flag when the CRC error occurs; determining a fault address based on the error flag; and mapping the fault address to one of non-fault spare addresses of the spare address area when the fault address is an address of the real address area.
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公开(公告)号：US11317488B2
公开(公告)日：2022-04-26
申请号：US17227994
申请日：2021-04-12
发明人： Jang Hyuck Lee , Hyun Mo Ahn , Byoung Kwon An
IPC分类号： H05B45/10 , H05B45/325 , H05B45/375 , H05B47/16
摘要： A switching control circuit configured to turn on a driving switching element by providing a gate signal to the driving switching element connected in series to an LED includes the switching control circuit configured to divide a PWM dimming signal into a normal PWM dimming section and a low PWM dimming section based on a timing selection signal, provide the gate signal of a first frequency to the driving switching element in the normal PWM dimming section, and provide the gate signal of a second frequency, greater than the first frequency, in the low PWM dimming section.
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公开(公告)号：US11289345B2
公开(公告)日：2022-03-29
申请号：US16387162
申请日：2019-04-17
发明人： Jo Han Kim , Hee Jin Park , Kyeong Su Kim , Jae Jin Lee
IPC分类号： H01L23/42 , H01L21/56 , H01L23/373 , H01L23/433 , H01L21/48
摘要： A method for manufacturing a heat releasing semiconductor chip package includes attaching a first surface of a semiconductor chip onto an insulating film, injecting a coating liquid onto a second surface of the semiconductor chip to form a liquefied coating layer and curing the liquefied coating layer to form a heat releasing layer. The coating liquid includes a liquefied molding compound for heat releasing and fine alumina particles. Therefore, the heat releasing semiconductor chip package and method for manufacturing the semiconductor chip package form a heat releasing layer in direct contact with the semiconductor chip to maximize a heat releasing effect.
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公开(公告)号：US11233517B2
公开(公告)日：2022-01-25
申请号：US16918233
申请日：2020-07-01
发明人： Yong Sup Lee , Gil Sung Roh
摘要： An auto trimming device includes an oscillator configured to generate an oscillator clock signal, a subtractor configured to receive an expected value for a target frequency and the oscillator clock signal, configured to output a difference value between the expected value and the oscillator clock signal, an index value selector configured to calculate a unit index value using the difference value and configured to detect and output a target index value from the unit index value, an index value register configured to output an oscillator trimming code corresponding to the target index value to the oscillator, and an embedded memory configured to store the oscillator trimming code as a target oscillator trimming code for the target frequency.
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公开(公告)号：US11233000B2
公开(公告)日：2022-01-25
申请号：US16503897
申请日：2019-07-05
发明人： Jae Sik Choi , Do Young Kim , Jin Won Jeong , Hye Ji Lee
IPC分类号： H01L23/498 , H01L23/528 , H01L27/12
摘要： A semiconductor package includes a first metal interconnection disposed in a semiconductor chip, a first bump group configured to be connected to the first metal interconnection, a first inner lead pattern group configured to be connected to the first bump group, a second metal interconnection disposed in the semiconductor chip, a second bump group configured to be connected to the second metal interconnection; and a second inner lead pattern group configured to be connected to the second bump group, wherein a density of the first metal interconnection is greater than a density of the second metal interconnection, such that a first pitch of the first lead pattern group is greater than a second pitch of the second lead pattern group.
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公开(公告)号：US20220005733A1
公开(公告)日：2022-01-06
申请号：US17231214
申请日：2021-04-15
发明人： Jin Won JEONG , Jang Hee LEE , Young Hun JUN , Jong Woon LEE , Jae Sik CHOI
摘要： A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.
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