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    METHOD TO FORM SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE THEREOF
    2.
    发明公开
    METHOD TO FORM SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE THEREOF 审中-公开

    公开(公告)号：US20230317526A1

    公开(公告)日：2023-10-05

    申请号：US17657835

    申请日：2022-04-04

    申请人： HeFeChip Corporation Limited

    发明人： LIANG LI ,  Chun Yu Wong ,  John Zhang ,  HUANG LIU ,  Sunil Singh ,  Heng Yang

    IPC分类号： H01L21/84 ,  H01L27/12

    CPC分类号： H01L21/845 ,  H01L27/1211

    摘要： The present invention proposes a semiconductor device. The semiconductor device includes a first and a second transistor sets, a fin pattern, a rare earth oxide layer and an insulation layer. The first and a second transistor sets commonly have at the bases thereof a buried oxide layer (BOX), wherein the first transistor set has a rare earth oxide. The fin pattern on the BOX within a first region for the first transistor set and a second region for the second transistor set. The rare earth oxide layer includes the rare earth oxide and is formed on the BOX and the fin pattern in the first region. The insulation layer is formed on the rare earth oxide layer in the first region, the BOX and the fin pattern in the second region.

    Magnetic memory device and method for manufacturing the same
    5.
    发明授权
    Magnetic memory device and method for manufacturing the same 有权

    公开(公告)号：US11177431B2

    公开(公告)日：2021-11-16

    申请号：US16701066

    申请日：2019-12-02

    申请人： HeFeChip Corporation Limited

    发明人： Geeng-Chuan Chern

    IPC分类号： H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01F10/32 ,  H01L27/22 ,  H01L43/12 ,  H01F41/34

    摘要： A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

    One-time programmable memory device and method for operating the same
    7.
    发明授权
    One-time programmable memory device and method for operating the same 有权

    公开(公告)号：US11074985B1

    公开(公告)日：2021-07-27

    申请号：US16801121

    申请日：2020-02-25

    申请人： HeFeChip Corporation Limited

    发明人： Geeng-Chuan Chern

    IPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/112

    摘要： A semiconductor device including at least an OTP unit cell is disclosed. The OTP unit cell includes a read select transistor, a data storage transistor serially connected to the read select transistor, and a program select transistor. The drain of the program select transistor is electrically coupled to the gate of the data storage transistor. The programming path for programming the three-transistor unit cell is different from the reading path for reading the OTP unit cell.

    SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20210118888A1

    公开(公告)日：2021-04-22

    申请号：US16658135

    申请日：2019-10-20

    申请人： HeFeChip Corporation Limited

    发明人： John Zhang ,  Yanzun Li ,  GuoLiang Zhu ,  Tongqing Chen ,  Huang Liu

    IPC分类号： H01L27/108

    摘要： A semiconductor device including a silicon-on-insulator (SOI) wafer comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer. At least a trench capacitor is disposed in a trench of the SOI wafer. The trench capacitor penetrates through the buried oxide layer and extends into the doped silicon substrate. At least a select transistor is disposed on the silicon device layer. The select transistor includes a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded contact is disposed atop the trench capacitor to electrically couple the drain doping region of the select transistor with an inner electrode of the trench capacitor.

    OPC MODELING METHOD
    10.
    发明公开
    OPC MODELING METHOD 审中-公开

    公开(公告)号：US20240192609A1

    公开(公告)日：2024-06-13

    申请号：US18076814

    申请日：2022-12-07

    申请人： HeFeChip Corporation Limited

    发明人： Yinuo PAN ,  Yingfang WANG ,  Keeho KIM ,  Norman S. CHEN ,  Eric S. PARENT

    IPC分类号： G03F7/20 ,  G06F30/30

    CPC分类号： G03F7/70441 ,  G03F7/705 ,  G06F30/30 ,  G06F2111/06

    摘要： An OPC modeling method is disclosed, which includes: step S1: determining optical model parameters and resist model parameters; step S2: obtaining a plurality of parameter combinations by stochastically choosing values for the parameters; step S3: performing photolithography simulations and etching wafers and calculating RMS values of differences between simulated CDs and etching CDs and BCE values of the CDs; step S4: evaluating the values according to Pareto principle and calculating Pareto optimum to N-th-best Pareto suboptimum sets to prioritize the plurality of parameter combinations in a descending order; step S5: applying a genetic algorithm with position-based crossover and/or mutation to the plurality of parameter combinations, to obtain new parameter combinations; and step S6: iterating steps S3 to S5 on the new parameter combinations until a number of iterations reaches a first predetermined value and using highest prioritized ones of parameter combinations resulting from a last iteration for OPC modeling.