公开(公告)号：US08362567B2

公开(公告)日：2013-01-29

申请号：US12309245

申请日：2007-07-12

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Rihito Kuroda

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Rihito Kuroda

IPC分类号： H01L21/70

CPC分类号： H01L29/045 ,  H01L21/02057 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/518 ,  H01L29/785 ,  H01L2029/7857

摘要： In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10−11 Ωcm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.

摘要翻译： 在半导体装置中，以峰 - 谷（PV）值为单位，平坦度为0.3nm以下的程度是通过在加有荧光的状态下加氢的超纯水冲洗硅表面而实现的 通过在电极和硅之间设定0.2eV以下的功函数差来实现10-11＆OHgr·cm 2以下的接触电阻。 因此，半导体器件可以在10GHz或更高的频率上工作。

公开(公告)号：US08268735B2

公开(公告)日：2012-09-18

申请号：US12223385

申请日：2007-01-30

申请人： Tadahiro Ohmi ,  Hitoshi Morinaga

发明人： Tadahiro Ohmi ,  Hitoshi Morinaga

IPC分类号： H01L21/02

CPC分类号： H01L21/02052 ,  H01L21/02074

摘要： Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved.

摘要翻译： 用液体进行表面处理，同时将半导体表面从光屏蔽。 当在诸如清洁，蚀刻和半导体表面的显影的湿法中使用该方法进行表面处理时，可以降低表面微粗糙度的增加。 因此，提高了半导体器件的电特性和产量。

公开(公告)号：US20120146102A1

公开(公告)日：2012-06-14

申请号：US13372159

申请日：2012-02-13

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Rihito Kuroda

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Rihito Kuroda

IPC分类号： H01L29/04 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/78654 ,  H01L29/78696

摘要： An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm−3 to achieve a large gate voltage swing.

摘要翻译： 累积模式晶体管的沟道区域中的半导体层的杂质浓度高于2×1017cm-3，以实现大的栅极电压摆动。

公开(公告)号：US07686600B2

公开(公告)日：2010-03-30

申请号：US10591430

申请日：2005-02-14

申请人： Tadahiro Ohmi

发明人： Tadahiro Ohmi

IPC分类号： F01C19/00 ,  F03C2/00

CPC分类号： F04D19/04 ,  F04C18/16 ,  F04C27/009 ,  F04C2220/30 ,  F04D29/102 ,  Y10S277/935 ,  Y10S277/936

摘要： Abstract A shaft seal structure (17) is provided around an outer circumferential surface of the bearing member (16M, 16FM) located on the cylinder inside of each of the screw rotors (13M, 13FM). The shaft seal structure (17) forms a static pressure seal. A seal gas is introduced between the outer circumferential surfaces of the bearing members (16M, 16FM) and the inner circumferential surfaces (7) of the rotor cylinders of the screw rotors (13M, 13FM) through the bearing members (16M, 16FM).

摘要翻译： 摘要设置在位于各螺杆转子（13M，13FM）的气缸内部的轴承部件（16M，16FM）的外周面周围的轴密封结构（17）。 轴密封结构（17）形成静压密封。 密封气体通过轴承部件（16M，16FM）被引导到轴承部件（16M，16FM）的外周面与螺杆转子（13M，13FM）的转子缸体的内周面（7）之间。

公开(公告)号：US20100038722A1

公开(公告)日：2010-02-18

申请号：US12604015

申请日：2009-10-22

申请人： Takefumi NISHIMUTA ,  Hiroshi MIYAGI ,  Tadahiro OHMI ,  Shigetoshi SUGAWA ,  Akinobu TERAMOTO

发明人： Takefumi NISHIMUTA ,  Hiroshi MIYAGI ,  Tadahiro OHMI ,  Shigetoshi SUGAWA ,  Akinobu TERAMOTO

IPC分类号： H01L27/092

CPC分类号： H01L29/7851 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L29/045

摘要： A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.

摘要翻译： 形成在半导体衬底上的MIS晶体管被假设为包括半导体衬底（702,910），该半导体衬底包括在主平面上的表面上具有至少两个不同晶面的突出部分（704,910B），栅极绝缘体（708 ，920B），用于覆盖构成所述突出部分的表面的所述至少两个不同晶面的每一个的至少一部分;栅电极（706,930B），包括在构成所述表面的所述至少两个不同晶面中的每一个上 所述突出部分与所述至少两个不同平面夹住所述栅极绝缘体，以及形成在所述突出部分中的所述至少两个不同晶面中的每一个的单导电型扩散区域（710a，710b，910c，910d） 并分别形成在栅电极的两侧。 这种配置允许控制元件面积的增加和通道宽度的增加。

公开(公告)号：US20090267122A1

公开(公告)日：2009-10-29

申请号：US12385868

申请日：2009-04-22

申请人： Tadahiro Ohmi ,  Ichiro Takahashi

发明人： Tadahiro Ohmi ,  Ichiro Takahashi

IPC分类号： H01L29/51 ,  H01L21/28

CPC分类号： H01L21/02192 ,  C23C14/024 ,  C23C14/08 ,  C23C14/5826 ,  H01G7/06 ,  H01J37/32192 ,  H01J37/32724 ,  H01J2237/2001 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/02244 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/55 ,  H01L29/40111 ,  H01L29/78391

摘要： A semiconductor device has a substrate, an insulator, an yttrium oxide film, a ferroelectric film (STN film), and an upper electrode.

摘要翻译： 半导体器件具有衬底，绝缘体，氧化钇膜，铁电体膜（STN膜）和上电极。

公开(公告)号：US07528074B2

公开(公告)日：2009-05-05

申请号：US10588698

申请日：2005-02-02

申请人： Tadahiro Ohmi ,  Tetsuya Goto

发明人： Tadahiro Ohmi ,  Tetsuya Goto

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31116 ,  H01L21/02063 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76814

摘要： During etching of a contact hole, not only the energy of ion irradiation but also the gas composition are altered to change the etching from a high-rate etching to a low-rate etching, thereby reducing the damage. In the low-rate etching where the gas composition is also altered, a firm fluorocarbon film is formed on the bottom of the contact hole, and the etching can be carried out while protecting the silicon surface. Consequently, inactivation of the impurities doped in the silicon surface can be prevented.

摘要翻译： 在蚀刻接触孔期间，不仅改变了离子辐射的能量，而且改变了气体组成，从而将蚀刻从高速蚀刻改变为低速蚀刻，从而减少了损伤。 在气体组成也变化的低速蚀刻中，在接触孔的底部形成坚固的碳氟膜，并且可以在保护硅表面的同时进行蚀刻。 因此，可以防止在硅表面中掺杂的杂质失活。

公开(公告)号：US07474383B2

公开(公告)日：2009-01-06

申请号：US10543454

申请日：2004-01-28

申请人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Kiwamu Takehisa

发明人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Kiwamu Takehisa

IPC分类号： G03B27/54 ,  G03B27/52

CPC分类号： G03F7/70283 ,  G03F7/70291

摘要： Laser light in a pattern reflected by a two-dimensional array micromirror 106 that is controlled on the basis of mask data of a mask pattern data output device 107 forms an enlarged pattern 110. This enlarged pattern is projected in a reduced manner onto a mask substrate 109 through a reduction-projection optical system 102, thereby forming a lithography pattern 111. Since a large number of patterns are written in an instant by the two-dimensional array micromirror 106, a time required for lithography the entire mask pattern is extremely shortened as compared with a conventional one. As a result, the mask cost can be largely reduced.

摘要翻译： 由基于掩模图案数据输出装置107的掩模数据控制的由二维阵列微镜106反射的图案的激光形成放大图案110.该放大图案以减小的方式投影到掩模基板上 通过缩小投影光学系统102，从而形成光刻图案111.由于通过二维阵列微镜106瞬时写入大量图案，因此平版印刷整个掩模图案所需的时间被极大地缩短为 与传统的相比。 结果，掩模成本可以大大降低。

公开(公告)号：US07312415B2

公开(公告)日：2007-12-25

申请号：US10706423

申请日：2003-11-10

申请人： Tadahiro Ohmi ,  Takahisa Nitta ,  Masaki Hirayama ,  Haruyuki Takano ,  Ryu Kaiwara

发明人： Tadahiro Ohmi ,  Takahisa Nitta ,  Masaki Hirayama ,  Haruyuki Takano ,  Ryu Kaiwara

IPC分类号： B23K10/00

CPC分类号： H01J37/32238 ,  C23C16/511 ,  H01J37/32192 ,  H01J37/3244 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02197 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/31675 ,  H01L21/31691

摘要： A plasma device which is provided with a container, a gas supply system, and an exhaust system. The container is composed of a first dielectric plate made of a material capable of transmitting microwaves. An antenna for radiating microwaves is located on the outside of the container, and an electrode for holding an object to be treated is located inside the container. The microwave radiating surface of the antenna and the surface of the object to be treated with plasma are positioned in parallel and opposite to each other. A wall section of the container other than that constituting the first dielectric plate is composed of a member of a material having electrical conductivity higher than that of aluminum, or the internal surface of the wall section is covered with the member. The thickness (d) of the member is larger that (2/μ0σ)1/2, where σ, μ0 and ω respectively represent the electrical conductivity of the member, the permeability of vacuum and the angular frequency of the microwaves radiated from the antenna.

摘要翻译： 设置有容器，气体供给系统和排气系统的等离子体装置。 容器由能够传输微波的材料制成的第一电介质板组成。 用于辐射微波的天线位于容器的外部，并且用于保持待处理物体的电极位于容器内部。 天线的微波辐射表面和待处理物体的表面等离子体彼此平行并相对定位。 容器的除构成第一电介质板之外的壁部分由导电率高于铝的材料的构件构成，或者壁部的内表面被构件覆盖。 该部件的厚度（d）大于（2 /μS≤Sigma）1/2，其中σ，μ0和ω 分别表示构件的导电性，真空的磁导率和从天线辐射的微波的角频率。

公开(公告)号：US20070252243A1

公开(公告)日：2007-11-01

申请号：US11664279

申请日：2004-10-10

申请人： Tadahiro Ohmi ,  Akihiro Morimoto

发明人： Tadahiro Ohmi ,  Akihiro Morimoto

IPC分类号： H01L29/04 ,  H01L21/00 ,  H01L21/44

CPC分类号： H01L29/7813 ,  H01L21/84 ,  H01L27/12 ,  H01L29/045 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/744 ,  H01L29/78603 ,  H01L2924/0002 ,  H05K1/053 ,  H01L2924/00

摘要： As a substrate for a semiconductor device, a metal substrate is used, and the metal substrate is composed of a metal base body made of a first metal and a connecting metal layer made of a second metal for covering the metal base body. The substrate has a structure wherein a diffusion preventing layer for preventing diffusion of the first metal is provided on the connecting metal layer.

摘要翻译： 作为半导体装置的基板，使用金属基板，金属基板由第一金属制的金属基体和由覆盖金属基体的第二金属构成的连接金属层构成。 基板具有其中在连接金属层上设置防止第一金属扩散的扩散防止层的结构。