公开(公告)号：US20050176208A1

公开(公告)日：2005-08-11

申请号：US11029648

申请日：2005-01-06

Applicant: Hiroaki Uchida

Inventor： Hiroaki Uchida

IPC: H01L21/00 ,  H01L21/86 ,  H01L27/12

CPC classification number: H01L27/12 ,  H01L21/86 ,  Y10S438/975

Abstract: The present invention provides a semiconductor wafer comprising an insulated board of sapphire or the like having translucency, which is provided with a positioning orientation flat at a peripheral portion thereof, and a silicon thin film formed over the entire one surface of the insulated board. In the semiconductor wafer, ions are implanted in an area containing the orientation flat at a peripheral portion of the silicon thin film to amorphize silicon. Thus, the translucency at the amorphized spot is eliminated and accurate positioning using the conventional optical sensor can be performed.

Abstract translation: 本发明提供了一种半导体晶片，其包括半导体的蓝宝石等的绝缘板，其在其周边部分设置有定位取向平面，以及形成在绝缘板的整个表面上的硅薄膜。 在半导体晶片中，将离子注入到在硅薄膜的周边部分包含定向平面的区域中以将硅非晶硅化。 因此，消除了非晶化点处的半透明度，并且可以执行使用常规光学传感器的精确定位。

公开(公告)号：US20050104176A1

公开(公告)日：2005-05-19

申请号：US10992145

申请日：2004-11-18

Applicant: Paul Rodney ,  James Masino ,  Christopher Golla ,  Roger Schultz ,  James Freeman

Inventor： Paul Rodney ,  James Masino ,  Christopher Golla ,  Roger Schultz ,  James Freeman

IPC: B81B7/00 ,  E21B20060101 ,  E21B7/00 ,  E21B45/00 ,  G01V20060101 ,  G01V3/08 ,  H01L20060101 ,  H01L21/86 ,  H01L23/02 ,  H01L27/12 ,  H01Q20060101

CPC classification number: E21B47/0002 ,  B81B2207/115 ,  E21B47/011 ,  G01V1/40 ,  H01L21/86 ,  H01L23/3157 ,  H01L27/12 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In at least some embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit fabricated on a silicon carbide substrate, and a thick passivation layer. In other embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit formed from silicon located on a sapphire substrate, and a thick passivation layer. The electronic devices may be implemented in the context of hydrocarbon drilling and production operations.

Abstract translation: 在至少一些实施例中，适于在超过200℃的温度下使用的电子器件可以包括在碳化硅衬底上制造的集成电路和厚钝化层。 在其它实施例中，适于在超过200℃的温度下使用的电子器件可以包括由位于蓝宝石衬底上的硅形成的集成电路和厚钝化层。 电子设备可以在碳氢化合物钻探和生产操作的背景下实现。

公开(公告)号：US20050087742A1

公开(公告)日：2005-04-28

申请号：US10969869

申请日：2004-10-22

Applicant: Youn Chang ,  Heung Cho

Inventor： Youn Chang ,  Heung Cho

IPC: G02F1/1368 ,  G02F1/1345 ,  G02F1/136 ,  G02F1/1362 ,  G09F9/30 ,  G09F9/35 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L21/86 ,  H01L27/12 ,  H01L29/786 ,  H01L29/04

CPC classification number: H01L27/1288 ,  G02F1/1362 ,  G02F2001/136231 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/66765

Abstract: A thin film transistor substrate for a display device having a plurality of thin film transistors and pixel electrodes connected to the thin film transistors, said thin film transistor substrate includes: a plurality of pad electrodes in a non-display area of the display device for applying signals to the plurality of thin film transistors in a non-display area of the display device; a protective film covering the pad electrodes in the non-display area; and a slit in the protective film adjacent to at least one of the plurality of pad electrodes.

Abstract translation: 一种用于显示装置的薄膜晶体管基板，具有连接到所述薄膜晶体管的多个薄膜晶体管和像素电极，所述薄膜晶体管基板包括：在显示装置的非显示区域中的多个焊盘电极，用于施加 信号到显示装置的非显示区域中的多个薄膜晶体管; 覆盖非显示区域中的焊盘电极的保护膜; 以及与所述多个焊盘电极中的至少一个相邻的保护膜中的狭缝。

公开(公告)号：US20050082623A1

公开(公告)日：2005-04-21

申请号：US10750752

申请日：2004-01-02

Applicant: Wein-Town Sun

Inventor： Wein-Town Sun

IPC: H01L21/86 ,  H01L29/76

CPC classification number: H01L21/86 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/49175

Abstract: A method for integrating a system on an isolation layer. A first isolation substrate including a first circuit deposition region and a first substrate-combining region, and a second isolation substrate including a second circuit deposition region and a second substrate-combining region are provided. Next, a first circuit and a, second circuit are respectively formed on the first circuit deposition region and the second circuit deposition region. Next, substrate-connecting elements are formed to connect the first substrate-combining region to the second substrate-combining region. Finally, electrical connecting elements are formed to electrically connect the first circuit and the second circuit.

Abstract translation: 一种在隔离层上集成系统的方法。 提供了包括第一电路淀积区域和第一衬底组合区域的第一隔离衬底和包括第二电路淀积区域和第二衬底组合区域的第二隔离衬底。 接下来，第一电路和第二电路分别形成在第一电路淀积区域和第二电路淀积区域上。 接下来，形成衬底连接元件以将第一衬底组合区域连接到第二衬底组合区域。 最后，形成电连接元件以电连接第一电路和第二电路。

公开(公告)号：US20050082537A1

公开(公告)日：2005-04-21

申请号：US10963822

申请日：2004-10-14

Applicant: Tatsuya Arao ,  Takeshi Noda ,  Takuya Matsuo ,  Hidehito Kitakado ,  Masanori Kyoho

Inventor： Tatsuya Arao ,  Takeshi Noda ,  Takuya Matsuo ,  Hidehito Kitakado ,  Masanori Kyoho

IPC: G02F1/1343 ,  G02F1/1368 ,  H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/77 ,  H01L21/86 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1259 ,  H01L29/6675 ,  H01L29/78621 ,  H01L29/78648

Abstract: A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed. The method for manufacturing the semiconductor device comprises the steps of: forming a semiconductor layer 3 having a source and a drain regions 10, 11, and LDD regions 16, 17; a gate insulating film 5; and a gate electrode 6; forming a first and a second interlayer insulating films 24, 25 over the gate electrode 6 and the gate insulating film 5; forming contact holes 25a, 25c to these interlayer insulating films so as to be located over each of the source region and the drain region; and an opening portion 25b to these interlayer insulating films so as to be located over the gate electrode and the LDD region; forming a second gate electrode 26b by a conductive film in the opening portion so as to cover the gate electrode and the LDD region; and a pixel electrode 26a over the second interlayer insulating film; removing the gate insulating film in the contact hole; and forming wirings 27, 28 connected to each the source region and the drain region.

Abstract translation: 公开了可以通过减少掩模数而降低成本的半导体器件，并且公开了一种用于制造半导体器件的方法。 制造半导体器件的方法包括以下步骤：形成具有源极和漏极区域10,11以及LDD区域16,17的半导体层3; 栅极绝缘膜5; 和栅电极6; 在栅极电极6和栅极绝缘膜5上形成第一和第二层间绝缘膜24,25; 向这些层间绝缘膜形成接触孔25a，25c，以便位于源极区域和漏极区域之上; 和这些层间绝缘膜的开口部分25b，以便位于栅电极和LDD区之上; 通过开口部中的导电膜形成第二栅电极26b，以覆盖栅电极和LDD区; 以及在第二层间绝缘膜上的像素电极26a; 去除接触孔中的栅极绝缘膜; 以及形成连接到每个源极区域和漏极区域的布线27,28。

公开(公告)号：US6040200A

公开(公告)日：2000-03-21

申请号：US834168

申请日：1997-04-14

Applicant: Yutaka Hayashi ,  Masaaki Kamiya ,  Yoshikazu Kojima ,  Hiroaki Takasu

Inventor： Yutaka Hayashi ,  Masaaki Kamiya ,  Yoshikazu Kojima ,  Hiroaki Takasu

IPC: G02F1/136 ,  G02F1/1335 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L21/86 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: G02F1/13454 ,  G02F1/136209 ,  G02F1/1368 ,  H01L21/84 ,  H01L21/86 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/66772 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78654 ,  G02F1/133512 ,  G02F2001/13613 ,  G02F2202/105 ,  Y10S148/012 ,  Y10S148/15 ,  Y10S438/977

Abstract: A method of fabricating a light valve device comprises forming a substrate having stacked layers including a light-shielding thin film layer, an insulating film, and a single crystalline semiconductor thin film stacked in this order on a transparent support substrate. A light-shielding layer pattern is formed by selectively etching the stacked layers. Thereafter, a switching element is formed comprised of a transistor having a channel region formed in the single crystalline semiconductor thin film and a main gate electrode covering the channel region. The channel region is provided over the light-shielding pattern layer to prevent light incident from the transparent support substrate from illuminating the channel region to suppress a photo-induced leakage current in the channel region. A transparent electrode is formed and is electrically connected to the switching element. An opposing substrate is then provided over the substrate at the side of the single crystalline semiconductor thin film, and an electro-optical material layer is interposed between the substrate and the opposing substrate.

Abstract translation: 一种制造光阀装置的方法包括在透明支撑基板上依次形成具有堆叠层的衬底，该层叠层包括遮光薄膜层，绝缘膜和单晶半导体薄膜。 通过选择性地蚀刻层叠层来形成遮光层图案。 此后，开关元件由具有在单晶半导体薄膜中形成的沟道区的晶体管和覆盖沟道区的主栅电极构成。 沟道区域设置在遮光图案层上，以防止从透明支撑衬底入射的光照射沟道区域，以抑制沟道区域中的光致感应漏电流。 形成透明电极并与开关元件电连接。 然后在单晶半导体薄膜侧面的衬底上设置相对的衬底，并且在衬底和相对衬底之间插入电光材料层。

公开(公告)号：US5926699A

公开(公告)日：1999-07-20

申请号：US89465

申请日：1998-06-02

Applicant: Yutaka Hayashi ,  Masaaki Kamiya ,  Yoshikazu Kojima ,  Hiroaki Takasu

Inventor： Yutaka Hayashi ,  Masaaki Kamiya ,  Yoshikazu Kojima ,  Hiroaki Takasu

IPC: G02F1/136 ,  G02F1/1335 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L21/86 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: G02F1/13454 ,  G02F1/136209 ,  G02F1/1368 ,  H01L21/84 ,  H01L21/86 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/66772 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78654 ,  G02F1/133512 ,  G02F2001/13613 ,  G02F2202/105 ,  Y10S148/012 ,  Y10S148/15 ,  Y10S438/977

Abstract: A method of fabricating a semiconductor device comprises the steps of sequentially forming a first gate electrode and an insulating film over a transparent support substrate, forming a through-hole in the insulating film, forming a semiconductor single crystal silicon thin film over the transparent support substrate by epitaxial growth in the through-hole of the insulating film, forming a transistor element having a channel region formed in the semiconductor single crystal silicon thin film, and forming a second gate electrode over and electrically insulated from the channel region of the transistor element.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：在透明支撑衬底上依次形成第一栅电极和绝缘膜，在绝缘膜中形成通孔，在透明支撑衬底上形成半导体单晶硅薄膜 通过在绝缘膜的通孔中进行外延生长，形成具有在半导体单晶硅薄膜中形成的沟道区的晶体管元件，并且在晶体管元件的沟道区上形成第二栅电极并将其电绝缘。

公开(公告)号：US5864162A

公开(公告)日：1999-01-26

申请号：US571661

申请日：1996-12-13

Applicant: Ronald E. Reedy ,  Mark L. Burgener

Inventor： Ronald E. Reedy ,  Mark L. Burgener

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/86 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786 ,  H01L29/8605 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/43

CPC classification number: H01L21/86 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02694 ,  H01L27/1112 ,  H01L27/12 ,  H01L27/1203 ,  H01L28/20 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78657 ,  H01L29/8605

Abstract: A thin silicon layer transistor integrated with a resistor. The resistor is self-aligned and contiguous with the transistor and is also formed of the same thin silicon layer as the transistor. This structure is particularly suitable for an SRAM circuit in order to simplify processing steps and to conserve area on SOS designs.

Abstract translation: 与电阻器集成的薄硅层晶体管。 电阻器是自对准的并且与晶体管相邻并且也由与晶体管相同的薄硅层形成。 该结构特别适用于SRAM电路，以简化处理步骤并节省SOS设计的面积。

公开(公告)号：US5663570A

公开(公告)日：1997-09-02

申请号：US444992

申请日：1995-05-19

Applicant: Ronald E. Reedy ,  Mark L. Burgener

Inventor： Ronald E. Reedy ,  Mark L. Burgener

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/86 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786 ,  H04Q9/00 ,  H01L29/06

CPC classification number: H01L28/20 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/76264 ,  H01L21/86 ,  H01L27/1112 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78657 ,  H01L21/76281 ,  Y02B60/50 ,  Y10S148/15 ,  Y10S438/967 ,  Y10S438/974 ,  Y10S438/977

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

公开(公告)号：US5658809A

公开(公告)日：1997-08-19

申请号：US403518

申请日：1995-03-13

Applicant: Sadao Nakashima ,  Katsutoshi Izumi ,  Norihiko Ohwada ,  Tatsuhiko Katayama

Inventor： Sadao Nakashima ,  Katsutoshi Izumi ,  Norihiko Ohwada ,  Tatsuhiko Katayama

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/31 ,  H01L21/762 ,  H01L21/86 ,  H01L27/00 ,  H01L27/12

CPC classification number: H01L21/26533 ,  H01L21/76243

Abstract: A method of producing an SOI substrate having a single-crystal silicon layer on a buried oxide layer in an electrically insulating state from the substrate by implanting oxygen ions into a single crystal silicon substrate and practicing an anneal processing in an inert gas atmosphere at high temperatures to form the buried oxide layer. After the anneal processing in which the thickness of the buried oxide layer becomes a theoretical value in conformity with the thickness of the buried oxide layer formed by the implanted oxygen, the oxidation processing of the substrate is carried out in a high temperature oxygen atmosphere.

Abstract translation: 一种通过将氧离子注入单晶硅衬底并在高温下在惰性气体气氛中进行退火处理的方法来制造具有电绝缘状态的掩埋氧化层上的单晶硅层的SOI衬底 以形成掩埋氧化物层。 在掩埋氧化物层的厚度成为与由注入氧形成的掩埋氧化物层的厚度一致的理论值的退火处理之后，基板的氧化处理在高温氧气氛中进行。