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    Leadframe-based semiconductor package for multi-media card
    81.
    发明申请
    Leadframe-based semiconductor package for multi-media card 失效
    用于多媒体卡的基于引线框架的半导体封装

    公开(公告)号：US20020140068A1

    公开(公告)日：2002-10-03

    申请号：US09820135

    申请日：2001-03-28

    Inventor： Ming-Hsun Lee ,  Ho-Yi Tsai

    IPC: H01L023/495 ,  H01L023/48 ,  H01L023/52 ,  H01L029/40

    CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

    Abstract: A leadframe-based semiconductor package is proposed for the packaging of a semiconductor device, such as a multi-media card (MMC) chipset. The proposed semiconductor package is characterized by the use of a leadframe, rather than BT substrate or film, as the chip carrier for MMC chipset. The leadframe includes a supporting bar, a chip-supporting structure arranged at a downset position in relation to the supporting bar; and a plurality of leads, each lead including an outer-lead portion and an inner-lead portion; wherein the outer-lead portion is levelly linked to the supporting bar, while the inner-lead portion is arranged beside the chip-supporting structure and linked to the outer-lead portion via an intermediate-lead portion. The leadframe can be either the type having die pad or the type having no die pad. In the case of the type having die pad, a semiconductor chip is mounted on the die pad; and in the case of the type having no die pad, one or more semiconductor chips are mounted over an elongated part of the inner-lead portions of the leads. The use of leadframe allows the MMC package to be manufactured without having to include a lidding process, so that the MMC manufacture can be carried out in a less complex and more cost-effective manner.

    Abstract translation: 提出了一种用于半导体器件（例如多媒体卡（MMC）芯片组）的封装的基于引线框的半导体封装。 所提出的半导体封装的特征在于使用引线框架而不是BT基板或薄膜作为用于MMC芯片组的芯片载体。 引线框架包括支撑杆，相对于支撑杆布置在降压位置处的芯片支撑结构; 以及多个引线，每个引线包括外部引线部分和内部引线部分; 其中，所述外引线部分与所述支撑杆平齐地连接，而所述内引线部分布置在所述芯片支撑结构旁边，并且经由中间引线部分连接到所述外引线部分。 引线框架可以是具有管芯焊盘的类型或者没有管芯焊盘的类型。 在具有管芯焊盘的类型的情况下，半导体芯片安装在管芯焊盘上; 并且在没有管芯焊盘的情况下，在引线的内引线部分的细长部分上安装一个或多个半导体芯片。 引线框的使用允许制造MMC封装，而不必包括封装工艺，以便MMC制造可以以较不复杂和更具成本效益的方式进行。

    Encapsulated die package with improved parasitic and thermal performance
    85.
    发明申请
    Encapsulated die package with improved parasitic and thermal performance 审中-公开
    封装的封装具有改进的寄生和热性能

    公开(公告)号：US20020121683A1

    公开(公告)日：2002-09-05

    申请号：US10085164

    申请日：2002-02-26

    Inventor： Stephen G. Kelly ,  Kenneth R. Philpot ,  Henricus Bernadus Antonius Giesen ,  William E. Doherty JR.

    IPC: H01L023/495 ,  H01L023/36

    CPC classification number: H01L33/62 ,  H01L23/3107 ,  H01L23/3737 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L33/642 ,  H01L33/647 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: An semiconductor device package (10) with improved thermal properties that limits unwanted parasitics and provides a more consistent distribution of parasitics from one device to another. The package of the present invention (10) is extremely compact and uses, in one embodiment, a minimal length of bond wires (20 and 22) between the terminals (14 and 16) and the attached device (30). The path length of the package (10) is reduced so as to represent only some fraction of a wavelength relative to the terminals (14 and 16) of the package (10). By reducing the length of the bond wires (20 and 22) and selecting the appropriate dielectric constant of the encapsulant (12), the invention provides a package (10) with a unique hexagonal structure that limits the effects of parasitics and provides good thermal dissipation. In a second and third embodiment of the present invention, the semiconductor device package (10) is useful in optoelectronic devices such light emitting diodes with an anode (71) and a cathode (72). The use of the novel design in this implementation also improves thermal properties and limits unwanted parasitics.

    Abstract translation: 一种具有改善的热性质的半导体器件封装（10），其限制不需要的寄生效应并且提供从一个器件到另一个器件的更一致的寄生效应分布。 本发明的封装（10）非常紧凑，在一个实施例中，在端子（14和16）和附接的装置（30）之间使用最小长度的接合线（20和22）。 包装（10）的路径长度减小，以便相对于包装（10）的端子（14和16）仅表示一部分波长。 通过减小接合线（20和22）的长度并选择密封剂（12）的适当介电常数，本发明提供了具有独特六边形结构的封装（10），其限制了寄生效应并提供良好的散热 。 在本发明的第二和第三实施例中，半导体器件封装（10）在诸如具有阳极（71）和阴极（72）的发光二极管的光电子器件中是有用的。 在本实施中使用新颖的设计还可以改善热性能并限制不必要的寄生效应。

    STRAPLESS LEAD FRAME
    86.
    发明申请
    STRAPLESS LEAD FRAME 审中-公开
    无缝导线框架

    公开(公告)号：US20020121682A1

    公开(公告)日：2002-09-05

    申请号：US09392899

    申请日：1999-09-09

    Inventor： RONALD B AZCARATE ,  PRIMITIVO A PALASI ,  PHILIP B SIMON

    IPC: H01L023/40 ,  H01L023/36 ,  H01L023/495

    CPC classification number: H01L24/06 ,  H01L23/49541 ,  H01L23/49558 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49179 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A lead frame that does not tie straps and a die bond pad is rectangular in shape, with the same number of lead frame leads (11) on opposite sides and a different number of lead frame lead frame leads (11) on adjacent sides. Lead frame leads (11) extend into the area in which the tie strap would normally be placed. A heat slug is (30) taped into the lead frame to provide a semiconductor die mount area. At least one lead (11) from one side of the lead frame, located where the tie strap is normally located, is connected via a bond wire (17a, 17b) to a bond pad (19) on the semiconductor die (18) on a side adjacent to the side where the lead frame lead is located.

    Abstract translation: 不绑扎带和芯片接合焊盘的引线框的形状为矩形，相邻侧上具有相同数量的引线框引线（11）和相邻侧上的不同数量的引线框引线框引线（11）。 引线框架引线（11）延伸到正常放置领带的区域。 （30）被插入引线框架以提供半导体管芯安装区域。 位于引线框架一侧的至少一个引线（11）通过接合线（17a，17b）连接到半导体管芯（18）上的接合焊盘（19）上 与引线框架引线所在的一侧相邻的一侧。

    Package structure of an integrated circuit
    89.
    发明申请
    Package structure of an integrated circuit 审中-公开
    集成电路的封装结构

    公开(公告)号：US20020096747A1

    公开(公告)日：2002-07-25

    申请号：US09770085

    申请日：2001-01-24

    Inventor： Nai Hua Yeh ,  Kuang Yu Fan ,  Mon Nan Ho ,  C. S. Cheng ,  C. H. Chen ,  Fu Yung Huang ,  Yung Sheng Chiu

    IPC: H01L023/495 ,  H01L023/48 ,  H01L023/52 ,  H01L029/40

    CPC classification number: H01L23/3114 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

    Abstract: A package structure of an integrated circuit is used for electrically connecting to a printed circuit board includes a substrate, an integrated circuit, a plurality of wires, two molded resins. The substrate has a lower surface formed with signal input terminals and signal output terminals, which are to be connected to the signal input terminals. The signal output terminals are electrically connected to the printed circuit board. The integrated circuit has a lower surface for mounting the integrated circuit to the upper surface of the substrate. The two sides on the lower surface of the integrated circuit formed with a plurality of bonding pads. While the integrated circuit mounted to the substrate, the bonding pads are exposed to the outside. The plurality of wires are electrically connected the bonding pads to the substrate. Thus, the signals from the integrated circuit can be transmitted to the substrate. Two molded resins are filled into the two sides of the integrated circuit and the substrate for sealing the plurality of wires to prevent the wires. Thus, the integrated circuit can be made thin, small, and slight.

    Abstract translation: 集成电路的封装结构用于电连接到印刷电路板，包括基板，集成电路，多根电线，两个模制树脂。 衬底具有形成有信号输入端子和信号输出端子的下表面，其将被连接到信号输入端子。 信号输出端子电连接到印刷电路板。 集成电路具有用于将集成电路安装到基板的上表面的下表面。 集成电路的下表面上的两侧形成有多个接合焊盘。 当安装到基板的集成电路时，接合焊盘暴露于外部。 多个导线将接合焊盘电连接到基板。 因此，来自集成电路的信号可以被传输到基板。 将两个模制树脂填充到集成电路的两侧和用于密封多根电线的基板以防止电线。 因此，集成电路可以制成薄，小，轻。

    Method and apparatus for assembling a conformal chip carrier to a flip chip
    90.
    发明申请
    Method and apparatus for assembling a conformal chip carrier to a flip chip 失效
    用于将保形芯片载体组装到倒装芯片的方法和装置

    公开(公告)号：US20020096746A1

    公开(公告)日：2002-07-25

    申请号：US10037536

    申请日：2002-01-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： David N. Cokely ,  Thomas M. Culnane ,  Lisa J. Jimarez ,  Miguel A. Jimarez ,  Li Li ,  Donald I. Mead

    IPC: H01L023/495

    CPC classification number: H01L24/81 ,  H01L21/6835 ,  H01L24/75 ,  H01L2224/75 ,  H01L2224/75755 ,  H01L2224/7598 ,  H01L2224/75983 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014

    Abstract: Fixtures for attaching a semiconductor chip to a substrate. The semiconductor chip has an array of joining material bumps, such as C4 solder balls. The substrate has an array of conductive pads corresponding to the array of joining material bumps. In a first embodiment the fixture has a body having a first cavity for containing the semiconductor chip and a second cavity in communication with the first cavity for containing the substrate. Whereby the substrate is placed over the semiconductor chip with the conductive pads opposing and in contact with the joining material bumps, such that during reflow of the joining material bumps, the weight of the substrate acts against the joining material bumps and aids in the attachment of the semiconductor chip to the substrate to form electrical connections therebetween. In a second embodiment the fixture has a first plate having a first opening for disposal of the semiconductor chip therein, a second plate stacked below the first plate and having a thickness substantially equal to the thickness of the substrate, the second plate further having a second opening opposing the first opening for disposal of the substrate therein, and a third plate stacked below the second plate such that the substrate is flattened in the second opening under the weight of the first plate thereby aiding in the attachment of the joining material bumps to their corresponding conductive pads during solder reflow to form electrical connections therebetween. Methods for use of the fixtures is also provided.

    Abstract translation: 用于将半导体芯片附接到基板的夹具。 半导体芯片具有连接材料凸块的阵列，例如C4焊球。 衬底具有对应于接合材料凸块阵列的导电焊盘阵列。 在第一实施例中，固定装置具有主体，该主体具有用于容纳半导体芯片的第一空腔和与第一空腔连通以容纳基板的第二空腔。 由此将衬底放置在半导体芯片上，其中导电焊盘与接合材料凸块相对并接触，使得在接合材料凸块的回流期间，衬底的重量抵抗接合材料凸起并且有助于附接 半导体芯片到基板以在它们之间形成电连接。 在第二实施例中，固定装置具有第一板，其具有用于在其中处理半导体芯片的第一开口，堆叠在第一板下方并且具有基本上等于衬底厚度的厚度的第二板，第二板还具有第二板 与第一开口相对地打开以处理其中的基板;以及第三板，堆叠在第二板下方，使得基板在第一板的重量下在第二开口中变平，由此辅助将接合材料凸块附接到它们 焊料回流期间相应的导电焊盘在其间形成电连接。 还提供了使用固定装置的方法。

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