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    SEMICONDUCTOR MEMORY DEVICE
    81.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20110141811A1

    公开(公告)日：2011-06-16

    申请号：US13033309

    申请日：2011-02-23

    Applicant: Takahiro Shimizu ,  Noboru Shibata

    Inventor： Takahiro Shimizu ,  Noboru Shibata

    IPC: G11C16/04

    CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641 ,  G11C2211/5643

    Abstract: A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.

    Abstract translation: 本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括具有多个存储单元的第一区域，每个存储器单元能够存储n位数据（n为自然数）和具有多个存储单元的第二区域 每个能够存储k比特数据（k> n：k是自然数），包括多个数据高速缓存的数据存储电路，以及控制该存储单元阵列和数据存储电路的控制电路 将从第一区域中的k / n个存储单元读取的k位数据存储到数据存储电路中的方式，并将k位数据存储到第二区域中的存储单元中。

    Non-Volatile Semiconductor Memory
    82.
    发明申请
    Non-Volatile Semiconductor Memory 有权
    非易失性半导体存储器

    公开(公告)号：US20110075488A1

    公开(公告)日：2011-03-31

    申请号：US12960882

    申请日：2010-12-06

    Applicant: Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    Inventor： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    IPC: G11C16/04

    CPC classification number: G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

    Abstract: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

    Abstract translation: 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

    Semiconductor memory device
    83.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07916534B2

    公开(公告)日：2011-03-29

    申请号：US11737373

    申请日：2007-04-19

    Applicant: Takahiro Shimizu ,  Noboru Shibata

    Inventor： Takahiro Shimizu ,  Noboru Shibata

    IPC: G11C16/04

    CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641 ,  G11C2211/5643

    Abstract: A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.

    Abstract translation: 本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括具有多个存储单元的第一区域，每个存储器单元能够存储n位数据（n为自然数）和具有多个存储单元的第二区域 每个能够存储k比特数据（k> n：k是自然数），包括多个数据高速缓存的数据存储电路，以及控制该存储单元阵列和数据存储电路的控制电路 将从第一区域中的k / n个存储单元读取的k位数据存储到数据存储电路中的方式，并将k位数据存储到第二区域中的存储单元中。

    Semiconductor memory device capable of executing high-speed read
    85.
    发明授权
    Semiconductor memory device capable of executing high-speed read 有权
    能够执行高速读取的半导体存储器件

    公开(公告)号：US07839686B2

    公开(公告)日：2010-11-23

    申请号：US11737413

    申请日：2007-04-19

    Applicant: Noboru Shibata

    Inventor： Noboru Shibata

    IPC: G11C16/04

    CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/565

    Abstract: A plurality of memory cells are arranged in a memory cell array. The plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines. A plurality of source lines are disposed along the plurality of bit lines. The plurality of source lines are connected respectively to sources of the plurality of memory cells at a time of data read.

    Abstract translation: 多个存储单元布置在存储单元阵列中。 多个存储单元连接到多个字线和多个位线。 多条源极线沿多条位线配置。 多个源极线在数据读取时分别连接到多个存储单元的源极。

    Nonvolatile memory system and associated programming methods
    88.
    发明授权
    Nonvolatile memory system and associated programming methods 有权
    非易失性存储器系统和相关编程方法

    公开(公告)号：US07602642B2

    公开(公告)日：2009-10-13

    申请号：US11730322

    申请日：2007-03-30

    Applicant: Jin-Hyeok Choi

    Inventor： Jin-Hyeok Choi

    IPC: G11C11/34

    CPC classification number: G11C8/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/3454 ,  G11C29/76 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2211/5642 ,  G11C2211/5643

    Abstract: A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to store a backup copy of previously programmed data from the multi-level flash memory cells when further programming of the multi-level flash memory cells fails. The backup copy of the previously programmed data is used to detect and correct any errors in the previously programmed data before reprogramming the previously programmed data to different multi-level memory cells in the nonvolatile memory system.

    Abstract translation: 非易失性存储器系统包括主机系统，存储器控制器和包括多级闪存单元的闪存芯片。 存储器控制器包括备用存储器，其适于在多级闪存单元的进一步编程失败时存储来自多级闪速存储器单元的先前编程的数据的备份副本。 先前编程的数据的备份副本用于检测和纠正先前编程的数据中的任何错误，然后将先前编程的数据重新编程到非易失性存储器系统中的不同多级存储器单元。

    Operation of a non-volatile memory array
    89.
    发明申请
    Operation of a non-volatile memory array 有权
    非易失性存储器阵列的操作

    公开(公告)号：US20090122610A1

    公开(公告)日：2009-05-14

    申请号：US12292240

    申请日：2008-11-14

    Applicant: Kobi Danon ,  Shai Eisen ,  Marcelo Krygier

    Inventor： Kobi Danon ,  Shai Eisen ,  Marcelo Krygier

    IPC: G11C16/04 ,  G11C16/06

    CPC classification number: G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2211/5643 ,  G11C2216/14

    Abstract: A cache programming operation which requires 2 SRAMs (one for the user and one for the array) may be combined with a multi-level cell (MLC) programming operation which also requires 2 SRAMs (one for caching the data and one for verifying the data), using only a total of two SRAMs (or buffers). One of the buffers (User SRAM) receives and stores user data. The other of the two buffers (Cache SRAM) may perform a caching function as well as a verify function. In this manner, if a program operation fails, the user can have its original data back so that he can try to reprogram it to a different place (address).

    Abstract translation: 需要2个SRAM（一个用于用户，另一个用于阵列）的高速缓存编程操作可以与多级单元（MLC）编程操作组合，其也需要2个SRAM（一个用于缓存数据，一个用于验证数据 ），仅使用两个SRAM（或缓冲器）。 其中一个缓冲区（User SRAM）接收并存储用户数据。 两个缓冲区（Cache SRAM）中的另一个可以执行缓存功能以及验证功能。 以这种方式，如果程序操作失败，用户可以将其原始数据返回，以便他可以尝试将其重新编程到不同的地方（地址）。

    Non-volatile memory with cache page copy
    90.
    发明授权
    Non-volatile memory with cache page copy 有权
    具有缓存页面复制的非易失性存储器

    公开(公告)号：US07499320B2

    公开(公告)日：2009-03-03

    申请号：US11683365

    申请日：2007-03-07

    Applicant: Yan Li

    Inventor： Yan Li

    IPC: G11C16/04

    CPC classification number: G06F12/0804 ,  G06F12/0882 ,  G06F2212/2022 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5642 ,  G11C2211/5643

    Abstract: A non-volatile memory and methods includes cached page copying using a minimum number of data latches for each memory cell. Multi-bit data is read in parallel from each memory cell of a group associated with a first word line. The read data is organized into multiple data-groups for shuttling out of the memory group-by-group according to a predetermined order for data-processing. Modified data are returned for updating the respective data group. The predetermined order is such that as more of the data groups are processed and available for programming, more of the higher programmed states are decodable. An adaptive full-sequence programming is performed concurrently with the processing. The programming copies the read data to another group of memory cells associated with a second word line, typically in a different erase block and preferably compensated for perturbative effects due to a word line adjacent the first word line.

    Abstract translation: 非易失性存储器和方法包括使用每个存储器单元的最小数量的数据锁存器进行缓存页复制。 从与第一字线相关联的组的每个存储器单元并行读取多位数据。 读取的数据被组织成多个数据组，用于根据用于数据处理的预定顺序逐个逐行地从存储器中逐出。 返回修改的数据以更新相应的数据组。 预定的顺序是这样的，当更多的数据组被处理并且可用于编程时，更多的编程状态可以被解码。 与处理同时执行自适应全序列编程。 编程将读取的数据复制到与第二字线相关联的另一组存储器单元，通常在不同的擦除块中，并且优选地由于与第一字线相邻的字线而被补偿的扰动效应。

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