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公开(公告)号：US20200091086A1
公开(公告)日：2020-03-19
申请号：US16694555
申请日：2019-11-25
发明人： Li-Hsien Huang , Hsien-Wei Chen , Ching-Wen Hsiao , Der-Chyang Yeh , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L23/31 , H01L23/498 , H01L21/48 , H01L23/538 , H01L21/683 , H01L23/00 , H01L25/10 , H01L25/00 , H01L21/768 , H01L23/522 , H01L21/56 , H01L21/78
摘要： A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.
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公开(公告)号：US20200035584A1
公开(公告)日：2020-01-30
申请号：US16588345
申请日：2019-09-30
发明人： Wei-Yu Chen , An-Jhih Su , Der-Chyang Yeh , Li-Hsien Huang , Ming Shih Yeh
IPC分类号： H01L23/485 , H01L21/683 , H01L23/538 , H01L25/00 , H01L23/522 , H01L21/48 , H01L21/56 , H01L25/10 , H01L23/528
摘要： In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.
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公开(公告)号：US10529650B2
公开(公告)日：2020-01-07
申请号：US15907474
申请日：2018-02-28
发明人： Wei-Yu Chen , An-Jhih Su , Der-Chyang Yeh , Li-Hsien Huang , Ming Shih Yeh
IPC分类号： H01L23/485 , H01L23/522 , H01L21/48 , H01L21/56 , H01L25/10 , H01L23/528 , H01L21/683 , H01L23/538 , H01L25/00 , H01L23/31 , H01L23/00 , H01L23/498
摘要： In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.
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公开(公告)号：US20200006248A1
公开(公告)日：2020-01-02
申请号：US16568983
申请日：2019-09-12
发明人： Chen-Hua Yu , Shin-Puu Jeng , Der-Chyang Yeh , Hsien-Wei Chen , Jie Chen
IPC分类号： H01L23/552 , H01L23/538 , H01L21/56 , H01L23/00 , H01L21/683 , H01L25/10 , H01L21/3205 , H01L21/768 , H01L23/58
摘要： A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line.
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公开(公告)号：US10510715B2
公开(公告)日：2019-12-17
申请号：US14968517
申请日：2015-12-14
发明人： Chen-Hua Yu , Chi-Hsi Wu , Der-Chyang Yeh , Hsien-Wei Chen , An-Jhih Su , Tien-Chung Yang
IPC分类号： H01L25/065 , H01L25/00
摘要： A semiconductor structure includes a first die, a second die horizontally disposed adjacent to the first die, a third die disposed over the first die and the second die, and a first dielectric material surrounding the first die and the second die, wherein a portion of the first dielectric material is disposed between the first die and the second die, and the third die is disposed over the portion of the dielectric.
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公开(公告)号：US10461036B2
公开(公告)日：2019-10-29
申请号：US16222219
申请日：2018-12-17
发明人： Chen-Hua Yu , An-Jhih Su , Chi-Hsi Wu , Der-Chyang Yeh , Ming Shih Yeh , Wei-Cheng Wu
IPC分类号： H01L23/538 , H01L21/56 , H01L25/16 , H01L23/00 , H01L21/768 , H01L21/3105 , H01L25/00 , H01L21/683 , H01L25/065 , H01L23/31
摘要： A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
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公开(公告)号：US10347606B2
公开(公告)日：2019-07-09
申请号：US15990055
申请日：2018-05-25
发明人： Chen-Hua Yu , An-Jhih Su , Wei-Yu Chen , Ying-Ju Chen , Tsung-Shu Lin , Chin-Chuan Chang , Hsien-Wei Chen , Wei-Cheng Wu , Li-Hsien Huang , Chi-Hsi Wu , Der-Chyang Yeh
IPC分类号： H01L21/56 , H01L25/00 , H01L25/065 , H01L21/48 , H01L21/78 , H01L23/31 , H01L23/498
摘要： A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
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公开(公告)号：US10297494B2
公开(公告)日：2019-05-21
申请号：US15640949
申请日：2017-07-03
发明人： Chen-Hua Yu , An-Jhih Su , Chi-Hsi Wu , Der-Chyang Yeh , Ming Shih Yeh , Jing-Cheng Lin , Hung-Jui Kou
IPC分类号： H01L21/768 , H01L23/522 , H01L23/538 , H01L23/498 , H01L23/48 , H01L23/00 , H01L21/48
摘要： A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
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公开(公告)号：US10290584B2
公开(公告)日：2019-05-14
申请号：US15725642
申请日：2017-10-05
发明人： Cheng-Hsien Hsieh , Li-Han Hsu , Wei-Cheng Wu , Hsien-Wei Chen , Der-Chyang Yeh , Chi-Hsi Wu , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/14 , H01L21/306 , H01L23/495 , H01L23/498 , H01L23/532 , H01L23/538
摘要： An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
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公开(公告)号：US20190139922A1
公开(公告)日：2019-05-09
申请号：US16221693
申请日：2018-12-17
发明人： Jing-Cheng Lin , Chen-Hua Yu , Jui-Pin Hung , Der-Chyang Yeh
IPC分类号： H01L23/00 , H01L23/538 , H01L23/498
摘要： A method comprises applying a metal-paste printing process to a surface-mount device to form a metal pillar, placing a first semiconductor die adjacent to the surface-mount device, forming a molding compound layer over the first semiconductor die and the surface-mount device, grinding the molding compound layer until a top surface of the first semiconductor die is exposed and forming a plurality of interconnect structures over the molding compound layer.
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