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公开(公告)号：US20220085280A1
公开(公告)日：2022-03-17
申请号：US17537793
申请日：2021-11-30
Inventor： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Sheng-Hung Shih , Tung-Sheng Hsiao , Wen-Ting Chu , Yu-Wen Liao , I-Ching Chen
IPC: H01L43/02 , H01L23/538 , H01L43/12 , H01L27/22 , H01L45/00 , H01L21/768 , H01L27/24 , H01L43/08
Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
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公开(公告)号：US20210384421A1
公开(公告)日：2021-12-09
申请号：US17411485
申请日：2021-08-25
Inventor： Chieh-Fei Chiu , Wen-Ting Chu , Yong-Shiuan Tsair , Yu-Wen Liao , Chin-Yu Mei , Po-Hao Tseng
IPC: H01L45/00 , H01L23/31 , H01L23/495 , H01L23/48
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.
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公开(公告)号：US20190259944A1
公开(公告)日：2019-08-22
申请号：US16398633
申请日：2019-04-30
Inventor： Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You , Wen-Ting Chu , Yu-Wen Liao
Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.
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公开(公告)号：US09853213B2
公开(公告)日：2017-12-26
申请号：US15380170
申请日：2016-12-15
Inventor： Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1666 , H01L45/1675
Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
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85.发明申请Resistive Switching Random Access Memory with Asymmetric Source and Drain 审中-公开具有不对称源和漏极的电阻式开关随机存取存储器公开(公告)号：US20170033159A1
公开(公告)日：2017-02-02
申请号：US15292964
申请日：2016-10-13
Inventor： Chin-Chieh Yang , Hsia-Wei Chen , Chih-Yang Chang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L27/24 , H01L29/78 , H01L21/266 , H01L29/66 , H01L21/265 , H01L45/00 , H01L29/08
CPC classification number: H01L27/2436 , H01L21/26513 , H01L21/266 , H01L29/0847 , H01L29/66659 , H01L29/7835 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1625
Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage. The resistive element includes a resistive material layer. The resistive element further includes first and second electrodes interposed by the resistive material layer. The resistive element further includes a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element, wherein the FET includes asymmetric source and drain, the drain having a higher doping concentration than the source. The resistive memory element is coupled with the drain.
Abstract translation: 电阻随机存取存储器（RRAM）结构包括形成在半导体衬底上并被设计用于数据存储的电阻存储元件。 电阻元件包括电阻材料层。 电阻元件还包括由电阻材料层插入的第一和第二电极。 电阻元件还包括形成在半导体衬底上并与电阻性存储元件耦合的场效应晶体管（FET），其中FET包括不对称源极和漏极，漏极具有比源高的掺杂浓度。 电阻存储元件与漏极耦合。
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Patent Agency Ranking
86.发明授权Resistive switching random access memory with asymmetric source and drain 有权具有不对称源极和漏极的电阻式开关随机存取存储器公开(公告)号：US09478638B2
公开(公告)日：2016-10-25
申请号：US13795123
申请日：2013-03-12
Inventor： Chin-Chieh Yang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Chih-Yang Chang , Hsia-Wei Chen
CPC classification number: H01L27/2436 , H01L21/26513 , H01L21/266 , H01L29/0847 , H01L29/66659 , H01L29/7835 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1625
Abstract: The present disclosure provides one embodiment of a resistive random access memory (RRAM) structure. The RRAM structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage; and a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element. The FET includes asymmetric source and drain. The resistive element includes a resistive material layer and further includes first and second electrodes interposed by the resistive material layer.
Abstract translation: 本公开提供了电阻随机存取存储器（RRAM）结构的一个实施例。 RRAM结构包括形成在半导体衬底上并被设计用于数据存储的电阻性存储元件; 和场效应晶体管（FET），形成在半导体衬底上并与电阻式存储元件耦合。 FET包括不对称源极和漏极。 电阻元件包括电阻材料层，并且还包括由电阻材料层插入的第一和第二电极。
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公开(公告)号：US20160268507A1
公开(公告)日：2016-09-15
申请号：US15161443
申请日：2016-05-23
Inventor： Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L45/00
CPC classification number: H01L45/146 , G11C11/5678 , G11C14/0009 , G11C14/0045 , H01L45/08 , H01L45/1253 , H01L45/1616 , H01L45/1675
Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.
Abstract translation: 半导体结构包括存储区。 存储器结构设置在存储器区域上。 存储器结构包括第一电极，电阻变化层，保护间隔物和第二电极。 第一电极具有顶表面和存储区上的第一外侧壁表面。 电阻变化层具有第一部分和第二部分。 第一部分设置在第一电极的顶表面上，第二部分从第一部分向上延伸。 保护间隔物设置在第一电极的顶表面的一部分上并且围绕电阻变化层的第二部分。 保护间隔件可配置为保护电阻变化层中的至少一个导电路径。 保护间隔件具有基本上与第一电极的第一外侧壁表面对齐的第二外侧壁表面。
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公开(公告)号：US09431604B2
公开(公告)日：2016-08-30
申请号：US13714719
申请日：2012-12-14
Inventor： Yu-Wen Liao , Wen-Ting Chu , Kuo-Chi Tu , Chin-Chieh Yang , Chih-Yang Chang , Hsia-Wei Chen
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer.
Abstract translation: 本公开提供了一种电阻随机存取存储器（RRAM）单元及其制造方法。 RRAM单元包括电连接到晶体管的晶体管和RRAM结构。 RRAM结构包括具有通孔部分和顶部的底部电极，在底部电极上方的电阻材料层，并且具有与底部电极的顶部相同的宽度，以及位于电阻材料层上的顶部电极，并且具有 比电阻材料层的宽度小。
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公开(公告)号：US09236570B2
公开(公告)日：2016-01-12
申请号：US14617499
申请日：2015-02-09
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Hsia-Wei Chen , Yu-Wen Liao , Chin-Chieh Yang
CPC classification number: H01L45/1666 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1675 , Y10S438/90
Abstract: A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell.
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公开(公告)号：US09231205B2
公开(公告)日：2016-01-05
申请号：US13802078
申请日：2013-03-13
Inventor： Chin-Chieh Yang , Wen-Ting Chu , Yu-Wen Liao , Chih-Yang Chang , Hsia-Wei Chen , Kuo-Chi Tu , Ching-Pei Hsieh
CPC classification number: H01L45/1608 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.
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