摘要:
An image sensor array includes image sensors having photo TFTs to generate photocurrent in response to received images. The photo TFTs each have their respective gate electrodes shorted to source electrodes to increase generated photocurrent. Storage capacitors are coupled to each photo TFT and discharged upon generation of a photocurrent. Each storage capacitor is coupled to a readout TFT that passes a current from the storage capacitor to a data line. Data lines indicate location of the received image on the image sensor array.
摘要:
This invention is related to an active matrix liquid crystal display (AMLCD) or an X-ray imaging device having a high aperture ratio, and method of making same. The imager or display has an increased aperture ratio because electrodes are formed over dual insulating layers so as to overlap portions of the array address lines and/or TFTs. Both the manufacturability and capacitive crosstalk of the device are improved due to the use of a photo-imageable organic insulating layer between the pixel electrodes and the address lines. An intermediate inorganic insulating layer is provided between the photo-imageable organic insulating layer and the overlapped TFTs in order to prevent the organic insulating layer from directly contacting semiconductor material in the TFTs thereby reducing potential voltage swings.
摘要:
A liquid crystal display having an increased pixel aperture ratio is disclosed along with a method of making same. An array of a-Si TFTs is deposited on a transparent substrate. Subsequently, an organic insulating layer (e.g. Benzocyclobutene) and a corresponding array of pixel electrodes are deposited over the TFT array so that the pixel electrodes overlap the display address lines thereby increasing the display's pixel aperture ratio. The low dielectric constant &egr; (e.g. about 2.7) and relatively high thickness (e.g. greater than about 1.5 &mgr;m) of the insulating layer reduce the pixel electrode-address line parasitic capacitance CPL in the overlap areas thereby reducing cross-talk (or capacitive coupling) in the display. In sum, an increased pixel aperture ratio is achieved without sacrificing display performance.
摘要:
A thin film transistor (TFT) for a liquid crystal display (LCD) and method of making same is disclosed, the TFT having a source and drain electrode where at least one of the source and drain includes first and second conductive layers offset from one another by a distance .DELTA.L so that the resulting TFT channel length L.sub.T is equal to L.sub.T =L.sub.1,2 -.DELTA.L where L.sub.1,2 is either a channel length defined in the first conductive layer or a channel length defined in the second conductive layer. The TFT manufacturing process includes the steps of: a) providing a conductive gate layer and patterning same to form a gate electrode; b) depositing a substantially transparent conductive layer (e.g. ITO) and patterning same to form a pixel electrode; c) depositing and patterning a semiconductor layer (e.g. a-Si); a doped semiconductor contact layer; and a first source-drain conductive layer so as to form a TFT island or area; d) using a single photoresist to etch a channel in the first source-drain layer and a via in a gate insulating layer so as to expose the pixel electrode; and e) depositing and patterning a second source-drain layer over the via and the etched first source-drain layer so as to form a TFT with reduced channel length L.sub.T wherein the second source-drain layer contacts the pixel electrode through the via. At least one of, and preferably both, the source and drain electrodes include a portion of the first and second source-drain layers contacting but offset laterally from one another.
摘要:
A liquid crystal display including an array of thin film transistors. Each thin film device in the array includes gate, source and drain electrodes. At least one of the source and drain electrodes include first and second metal layers offset with respect to one another so as to reduce the channel length of the transistors. Because of the reduced TFT channel length, the TFT channel width can also be reduced while maintaining the same ON current. Thus, the gate-source capacitance is reduced which in turn reduces pixel flickering and image retention and improves gray level uniformity. The first and second source-drain metal layers are of different materials so that the etchant for the second metal does not etch the first metal layer deposited. The TFT may be either a linear TFT or a ring-shaped TFT according to different embodiments of this invention.
摘要:
A thin film transistor (TFT) array in an active matrix liquid crystal display (AMLCD) including a centrally located round source electrode completely surrounded by a substantially annular or circular shaped drain electrode. The geometric design of the TFT of this invention provides for a thin film transistor having a reduced parasitic capacitance and decreased photosensitivity. The TFTs of this invention are located at the intersections of gate and drain lines of an active matrix LCD array thereby increasing the size of the pixel display openings of the matrix array.
摘要:
A thin film transistor (TFT) having a reduced channel length and method of making same are disclosed for liquid crystal display (LCD) applications. The method of making the TFT includes the following process steps: (i) depositing and patterning the gate on a substrate; (ii) depositing and patterning an intrinsic a-Si layer, a n+ a-Si layer, and a source metal layer (e.g. Cr) over the gate; (iii) depositing and patterning an ITO layer to form a pixel electrode portion and a TFT source portion; (iv) etching the source metal layer so that it remains only under the ITO source portion so as to form the TFT source electrode; (v) depositing and patterning a metal (e.g. Mo) to form the drain of the TFT; and (vi) etching the n+ a-Si layer in the TFT channel area so that only the intrinsic semiconductor layer remains between the source and drain. The resulting TFT has a reduced channel length (e.g. less than about 4 .mu.m) less than the feature size of the lithography used so as to maximize I.sub.ON /C.sub.gs(ON) of the TFT. Maximizing I.sub.ON /C.sub.gs(ON) reduces pixel flickering, gray scale non-uniformity, and image retention in LCD applications.